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cl-cd1283 data book october 1996 version 2.0 features parallel port (peripheral-side) high-speed, bidirectional, multi-protocol parallel port: n hardware implementation of all modes of the ieee std (standard) 1284 speci?ation (including automatic negotiation) centronics a -compatible mode reverse byte mode reverse nibble mode ecp (extended capabilities port) mode with run-length encoding/decoding epp (enhanced parallel port) mode up to 2-mbytes/sec. transfer rate in ecp and epp modes n 64-byte parallel fifo with dma interface 64-byte fifo can accommodate up to 4 kbytes of com- pressed data with rle (run-length encoded) compression enabled n supports peripheral-side operation n data and control input/output pads support ieee std1284 level-2 interface speci?ation n cpu bus interface high-speed slave dma handshake interface three clocks per word dma transfers on-the-? data compression using rle (run-length encoded) encoding and decoding 8/16-bit data interface the cl-cd1283 is a multi-function interface control- ler for printers, scanners, tape-drives, set-top boxes, data acquisition, and other applications that require high-speed, bidirectional, parallel communication with a host computer. all modes of the ieee std 1284 standard signaling method for bidirectional parallel peripheral interface for personal comput- ers speci?ation are supported, including ecp, epp, reverse byte, reverse nibble, and compatible. with full support of this standard, the cl-cd1283 provides compatibility with all types of host parallel ports, including older centronics a , ibm a ps/2 a bidirectional, and the latest ieee 1284-compliant ports. the dedicated state-machine design provides the fastest possible response times to all host signal changes, with 100% guaranteed compliance to all ieee 1284 timing, protocol, and signaling (cont.) (cont.) overview f unct i ona l bl oc k di agram dma logic interrupt logic host interface compression/ decompression logic data mover logic 64 bytes level-2 electrical interface control state machine data pipeline fifo ieee 1284 peripheral parallel port general-purpose i/o port ieee 1284-compatible parallel interface controller
october 1996 data book v2.0 cl-cd1283 ieee 1284-compatible parallel interface controller 2 overview advantages unique features bene?s n supports ieee std 1284 speci?ation r multi-protocol bidirectional port for a wide range of applications. up to 2 mbytes/sec. transfer rate provides future connectivity with new host systems n hardware support of ieee std 1284 timings r reduces software complexity and guarantees speci?ation compliance. n 64-byte fifo r high throughput with reduced load on host cpu. n parallel port signals provide level-2 drive characteristics r direct connection to printer cable; reduces chip count. n dma channel r reduces host interface overhead. high-speed data movement between memory and parallel port. n ecp compression/decompression in hardware r reduces software complexity and increases throughput of compressed-data tranfers. byteswap input provides easy interface to both big- and little-endian systems vectored interrupts simplify interrupt service routines features (cont.) requirements. the cl-cd1283 device, operating at 25 mhz, has signal response times to support 2 mbytes/sec. transfers, provided that a comparably fast host parallel port is used. this performance headroom guarantees that the faster data rates of future host parallel port implementations will be sup- ported by peripheral applications using the cl-cd1283. in addition to the dedicated state machine, the cl-cd1283 provides slave dma support, and a 64-byte fifo to allow maximum total throughput performance. interrupts are generated based on status changes of the parallel port. note, however that interrupts are not generated by fifo threshold, or fifo full/empty conditions. the dma request signal can be used to generate interrupts as long as hardware and software implementation is handled correctly. if maximum performance is not a require- ment, the device can be monitored and controlled by polling its detailed status registers. another unique feature of the cl-cd128x series of devices is the dedicated hardware for rle compression/decompression in ecp mode. special logic is used to perform the ecp-rle compression/decompression ?n-the-? while data is moved to and from the fifo. all of these capabilities above and beyond the requirements of the ieee 1284 speci?ation permit the use of a less expensive microprocessor by reducing the required cpu bandwidth needed for the parallel port. to aid in the development of hardware and software, an evaluation kit ?complete with application notes and programmers guide ?is provided along with software examples and evaluation board schemat- ics. the isa add-in card is designed to demonstrate the capabilities of the cl-cd128x family of devices, and enables software developers to begin testing code while the system hardware is still in development. overview (cont.) general n system clock up to 25 mhz n cmos technology enables high speed and low power n available in a 100-pin pqfp package
cl-cd1283 ieee 1284-compatible parallel interface controller before beginning any new design with this device, please contact cirrus logic for the latest errata information. this data book is in reference to revision e or newer devices. see the back cover of this document for sales of?e locations and phone numbers. october 1996 3 data book v2.0 contents table of contents list of figures ................................ 5 list of tables................................... 6 revision history ............................. 6 conventions..................................... 7 1. pin information ............................... 8 1.1 pin diagram ............................................. 8 1.2 pin list ..................................................... 9 1.3 pin descriptions ..................................... 10 2. register summary ....................... 13 2.1 register summary tables ...................... 13 3. functional description............ 16 3.1 device architecture ................................ 16 3.2 cpu interface......................................... 16 3.2.1 read cycles.............................. 17 3.2.2 write cycles .............................. 17 3.2.3 service-acknowledge cycles.... 17 3.2.4 dma cycles .............................. 18 3.2.5 interrupts ................................... 19 3.2.6 dmareq* as interrupt source....................................... 19 3.2.7 daisy-chain con?urations ...... 19 3.3 parallel port service requests .............. 21 3.3.1 hardware-activated acknowledge ............................. 25 3.3.2 software-activated acknowledge ............................. 25 3.4 parallel port fifo and data pipeline ..... 25 3.4.1 ieee standard 1284 protocols ................................... 26 3.4.2 bus interface ............................. 26 3.4.3 parallel port fifo...................... 26 3.4.4 receive direction ...................... 27 3.4.5 receiving compressed data .... 27 3.4.6 stale data (stale, onechar, and timeout status bits).................. 27 3.4.7 transmit direction ..................... 28 3.5 parallel port overview............................ 29 3.5.1 terminology............................... 29 3.5.2 signal names............................29 3.5.3 state machine ...........................29 3.5.4 con?uration .............................29 3.5.5 interrupts ...................................30 3.5.6 manual mode ............................30 3.5.7 control signals..........................30 3.5.8 parallel port interface to the fifo ..........................................31 3.5.9 ieee 1284-protocol negotiations ..............................31 3.5.10 data transfers ...........................31 3.5.11 compatibility mode status ........31 3.6 ieee 1284 parallel protocol support .....32 3.6.1 compatibility mode....................32 3.6.2 reverse-nibble and reverse-byte modes .......................................32 3.6.3 id request ................................32 3.6.4 ecp mode.................................32 3.6.5 epp mode .................................33 3.7 protocol timing ......................................33 3.8 general-purpose i/o port ......................33 3.9 parallel port interface .............................33 3.10 hardware con?urations........................35 3.10.1 interfacing to an intel a microprocessor-based system ......................................36 3.10.2 interfacing to a motorola a microprocessor-based system ......................................37 4. programming..................................38 4.1 overview ................................................38 4.2 initialization ............................................38 4.2.1 device reset .............................38 4.2.2 service acknowledge handling ....................................41 4.3 ascii code tables .................................43 5. detailed register descriptions ...................................44 5.1 global registers.....................................44 5.1.1 access enable register ............44
data book v2.0 october 1996 4 contents cl-cd1283 ieee 1284-compatible parallel interface controller 5.1.2 global firmware revision code register..................................... 44 5.1.3 general-purpose i/o direction register..................................... 45 5.1.4 general-purpose i/o register..................................... 45 5.1.5 parallel interrupt register ......... 46 5.1.6 prescaler period register ......... 46 5.1.7 service request register ......... 47 5.2 virtual registers..................................... 48 5.2.1 end-of-service request register..................................... 48 5.2.2 parallel interrupt vector register..................................... 49 5.3 parallel pipeline registers ..................... 50 5.3.1 data error register ................... 50 5.3.2 dma buffer data register......... 51 5.3.3 holding register status register..................................... 52 5.3.4 host timeout value register..... 53 5.3.5 local interrupt vector register..................................... 54 5.3.6 parallel auxiliary control register..................................... 55 5.3.7 parallel channel reset register..................................... 56 5.3.8 parallel fifo control register..................................... 56 5.3.9 parallel fifo empty pointer register..................................... 57 5.3.10 parallel fifo fill pointer register..................................... 57 5.3.11 parallel fifo holding registers ................................... 58 5.3.12 parallel fifo quantity register..................................... 58 5.3.13 parallel fifo status register.... 59 5.3.14 parallel fifo threshold register..................................... 60 5.3.15 run-length count register ...... 60 5.3.16 stale data timer count register..................................... 61 5.3.17 stale data timer period register..................................... 61 5.4 parallel port registers............................ 62 5.4.1 epp address register .............. 62 5.4.2 input value register .................. 62 5.4.3 manual data register ............... 62 5.4.4 negotiation enable register ..... 63 5.4.5 negotiation status register ...... 64 5.4.6 ones detect register................ 65 5.4.7 output value register ............... 65 5.4.8 parallel channel interrupt enable register..................................... 66 5.4.9 parallel channel interrupt status register..................................... 66 5.4.10 parallel con?uration register..................................... 67 5.4.11 special command register ...... 68 5.4.12 short pulse register ................. 69 5.4.13 signal status register............... 70 5.4.14 zeros detect register ............... 70 5.5 special register ..................................... 70 5.5.1 reset command register......... 70 6. electrical specifications ....... 71 6.1 absolute maximum ratings ................... 71 6.2 recommended operating conditions .............................................. 71 6.3 dc characteristics ................................. 71 6.4 ac characteristics ................................. 73 6.4.1 asynchronous timing................ 73 6.4.2 synchronous timing.................. 81 7. package dimensions.................... 87 8. ordering information ............... 88 bit index............................................ 89 index .................................................. 91
october 1996 5 data book v2.0 contents cl-cd1283 ieee 1284-compatible parallel interface controller list of figures figure 3-1. functional block diagram ............................................................................................ .....................16 figure 3-2. internal address generation......................................................................................... ....................17 figure 3-3. cl-cd1283 daisy-chain con?uration .................................................................................. ..........20 figure 3-4. interrupt generation logic .......................................................................................... ......................22 figure 3-5. control signal generation........................................................................................... ......................24 figure 3-6. fifo data path functional diagram ?receive......................................................................... .......29 figure 3-7. fifo data path functional diagram: transmit......................................................................... .........30 figure 3-8. supported compatibility mode timing ................................................................................. .............32 figure 3-9. cable connection .................................................................................................... .........................34 figure 3-10. external buffer control............................................................................................ ..........................35 figure 3-11. sample system block diagram ........................................................................................ ................35 figure 3-12. intel a 80x86 family interface........................................................................................................ ....36 figure 3-13. motorola a 68020 interface............................................................................................................... .37 figure 4-1. flow diagram of the cl-cd1283 master initialization sequence.....................................................39 figure 4-2. polling flow chart.................................................................................................. ...........................42 figure 6-1. reset timing ........................................................................................................ .............................75 figure 6-2. clock timing ........................................................................................................ .............................75 figure 6-3. asynchronous read cycle timing ...................................................................................... ..............76 figure 6-4. asynchronous write cycle timing ..................................................................................... ...............77 figure 6-5. asynchronous service acknowledge cycle timing ....................................................................... ...78 figure 6-6a. asynchronous dma read cycle timing ................................................................................ ..........79 figure 6-6b. asynchronous dma read cycle timing (two back-to-back dma reads) .....................................79 figure 6-7a. asynchronous dma write cycle timing ............................................................................... ...........80 figure 6-7b. asynchronous dma write cycle timing ............................................................................... ...........80 figure 6-8. synchronous read cycle timing....................................................................................... ...............82 figure 6-9. synchronous write cycle timing ...................................................................................... ................83 figure 6-10. synchronous service acknowledge cycle timing ....................................................................... .....84 figure 6-11. synchronous dma write cycle timing (two back-to-back 3-cycle dma writes)............................85 figure 6-12. synchronous dma read cycle timing (two back-to-back 3-cycle dma reads) ...........................86
data book v2.0 october 1996 6 contents cl-cd1283 ieee 1284-compatible parallel interface controller list of tables table 2-1. global registers ..................................................................................................... .......................... 13 table 2-2. virtual registers .................................................................................................... ........................... 14 table 2-3. parallel pipeline registers .......................................................................................... ...................... 14 table 2-4. parallel port registers .............................................................................................. ........................ 15 table 2-5. special register..................................................................................................... ........................... 15 table 3-1. livr[2:0] encoding ................................................................................................... ........................ 24 table 3-2. system clock setup................................................................................................... ....................... 33 table 4-1. hexadecimal ?character.............................................................................................. .................. 43 table 4-2. decimal ?character.................................................................................................. ...................... 43 table 5-1. pivr[2:0] encoding ................................................................................................... ....................... 49 table 5-2. spr binary values to set 500-ns pulse widths ......................................................................... ...... 69 table 6-1. asynchronous timing reference parameters............................................................................. ...... 73 table 6-2. synchronous timing reference parameters .............................................................................. ...... 81 revision history major changes between the previous data book (dated july 1994) and this version are listed below. section revision 1 ring indication pins (ri2*, ri3*) added to pin diagram and descriptions provided. 3 interrupt generation logic diagram provided, figure 3-4. device usage caution added to figure 3-9. 5 register reset default values provided. 6 asynchronous timing values and diagrams provided. index a bit index has been added.
october 1996 7 data book v2.0 conventions cl-cd1283 ieee 1284-compatible parallel interface controller conventions abbreviations the use of ?bd indicates values that are ?o be determined? ?/a designates ?ot available? and ?/c indicates a pin that is a ?o connect? acronyms symbol units of measure c degree celsius hz hertz (cycles per second) kbyte kilobyte (1,024 bytes) khz kilohertz k w kilohm mbyte megabyte (1,048,576 bytes) mhz megahertz (1,000 kilohertz) m f microfarad m s microsecond (1,000 nanoseconds) ma milliampere ms millisecond (1,000 microseconds) ns nanosecond pv picovolt acronym de?ition ac alternating current bios basic input/output system cisc complex instruction set computer cmos complementary metal-oxide semiconductor dc direct current dma direct-memory access dram dynamic random-access memory ecp extended capibilities port epp enhanced parallel port fifo ?st in/?st out gpio general-purpose io hcmos high-performance complementary metal- oxide semiconductor hdlc high-level data link control ic integrated circuit idc instruction and data cache isa industry standard architecture lsb least-signi?ant bit mpu microprocessing unit msb most-signi?ant bit pio programmed i/o ppp point-to-point protocol pqfp plastic quad-?t pack ram random-access memory rle run-length encoded r/w read/write sdlc synchronous data link control sram static random-access memory swi software interrupt instruction tlb translation look-aside buffer ttb translation table base ttl transitor-transitor logic vram video random-access memory wb write buffer acronym de?ition
data book v2.0 october 1996 8 pin information cl-cd1283 ieee 1284-compatible parallel interface controller 1. pin information 1.1 pin diagram cl-cd1283 100-pin pqfp v cc gnd xflag perclk perbsy akdarq ninit hstclk hstbsy a_1284 pdben gnd gp[7] gp[6] gp[5] ds* r/w* dtack* cs* reset* gp[4] pullup1 pullup5 dpass* dgrant* gp[3] pullup2 pullup6 gnd db[15] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 80 79 78 77 76 73 72 74 75 71 70 68 67 65 63 62 61 60 59 58 57 55 53 52 51 69 66 64 56 54 gnd clk/2 v cc db[8] db[9] db[10] db[11] db[12] db[13] db[14] v cc dmaack* n/c n/c n/c n/c n/c n/c db[5] db[4] db[2] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd v cc ebdir pd[0] pd[1] pd[2] pd[7] db[1] db[6] pd[6] pd[5] pd[4] pd[3] dmareq* gp[0] db[0] gnd a[1] ndatav gp[2] pullup3 svcreqp* clk gp[1] pullup4 svcackp* n/c db[3] a[0] byteswap v cc db[7] gnd a[6] outen a[5] a[4] a[2] a[3] note: (*) denotes negative-true signal. ?/c indicates no connection; make no connection to these pins. pin names compatibility reverse nibble mode reverse byte mode ecp mode epp mode inputs a_1284 slctin* a_1284 a_1284 a_1284 nastrb hstbsy autofd* hstbsy hstbsy hstack ndstrb hstclk strobe* hstclk hstclk hstclk nwrite ninit init* ninit ninit nrevreq ninit outputs akdarq perror akdarq akdarq nakrev user1 perbsy busy perbsy perbsy perack nwait perclk ack* perclk perclk perclk intr ndatav fault* ndatav ndatav nperreq user2 xflag select xflag xflag xflag user3
october 1996 9 data book v2.0 pin information cl-cd1283 ieee 1284-compatible parallel interface controller 1.2 pin list the following naming conventions are used in the pin-assignment tables: l (*) after a name indicates that the signal is active-low l ? indicates the pin is input-only l ? indicates the pin is output-only l ?/o indicates the pin is bidirectional l ?d indicates an open-drain output that the user must tie to v cc through a pull-up resistor (usually about 1 k w ) l ?s indicates tristate l ?u indicates pull-up, which must also be tied to v cc through a 1-k w resistor (note that all six pu pins can be wire-or?d through the same pull-up resistor) l ?r indicates active release (pin drives high and releases to od) l a indicates ascending pin numbers l a ? indicates descending pin numbers pin name type number of pins pin numbers reset state a[6:0] i 7 84?0 byteswap i 1 82 clk i 1 73 clk/2 o 1 80 n/a cs* i 1 78 db[15:0] i/o 16 92?9, 2? ts ds* i 1 77 dtack* ar 1 75 ts outen i 1 83 reset* i 1 79 r/w* i 1 76 dmareq* o 1 13 high dmaack* i 1 12 svcreqp* od 1 68 high svcackp* i 1 69 dgrant* i 1 70 dpass* o 1 71 high pd[7:0] i/o 8 41?8 ts gp[7:0] i/o 8 53?0 ts a_1284 i 1 31 ninit i 1 34 hstbsy i 1 32 hstclk i 1 33 perbsy o 1 36 low perclk o 1 37 high akdarq o 1 35 low x?g o 1 39 low ndatav o 1 38 high ebdir o 1 49 high pdben o 1 51 low gnd i 7 1, 10, 30, 40, 52, 72, 91 pullup1 pu 1 61 pullup2 pu 1 62 pullup3 pu 1 63 pullup4 pu 1 64 pullup5 pu 1 66 pullup6 pu 1 67 v cc i5 11, 50, 65, 81, 100 pin name type number of pins pin numbers reset state
data book v2.0 october 1996 10 pin information cl-cd1283 ieee 1284-compatible parallel interface controller 1.3 pin descriptions symbol pin no. type description a[6:0] 84?0 i address bus: together with cs* or one of the svcack* inputs and ds*, this input selects an on-chip register for a read or write operation or an acknowledgment to a ser- vice request. byteswap 82 i byteswap: this input determines the byte order for 2-byte dma transfers and for writes to the dmabuf register. if byteswap is set to ?? data bus bits 15:8 are driven with the byte transferred ?st on the parallel port bus. data bus bits 7:0 are driven with the byte transferred second on the parallel port bus. if byteswap is set to ?? the data order is reversed, bits 7:0 are driven with the ?st byte transferred, and bits 15:8 are driven with the second byte transferred. clk 73 i system clock: this input has a 25 mhz maximum; 16 mhz is the recommended minimum for satisfactory device performance. clk/2 80 o system clock divided by two output: this signal is equivalent to the internal operating clock of the device. cs* 78 i active-low chip select: when active, the input cs* in conjunction with ds*, ini- tiates a i/o cycle with the cl-cd1283. cs* must be set to ? during dma read/write operations. db[15:0] 92?9, 2? i/o bidirectional data bus [15:0]: only dma transfers and writes to the dma buffer register are true 16-bit operations. during all register writes other than to the dma buffer register, only bits 7:0 are written to the addressed register. register reads dupli- cate the register contents on both the lower byte, bits 7:0, and upper byte, bits 15:8. ds* 77 i active-low data strobe: during an active i/o cycle, the input ds* strobes data into on-chip registers on write cycles or enables data onto the data bus during read cycles. ds* is ignored during dma operations. dtack* 75 ar active-low data transfer acknowledge: this output indicates: when the device has completed the requested i/o operation, and when the cycle may ?ish. this signal can be used to implement wait-state insertion for the local cpu. it is an active release output, driving to logic ? then releasing to od. dtack* must be tied to exter- nal v cc with a pull-up resistor. dtack* is not activated on dma cycles. outen 83 i output enable: this pin must be set to ? to enable output pin functions. when outen is set to ?? it forces all pins that can act as outputs to remain in a tristate con- dition. outen is used as a test input and is not normally used in an end application. user designs should tie this pin to v cc through a pull-up resistor. reset* 79 i active-low reset input: initializes the device to the default condition. all internal registers are set to their reset condition and all transfer operations are set to the default state. r/w* 76 i read/write*: this pin must be set to ? for a register read operation and set to ? for a register write operation. this input is ignored for dma operations. dmareq* 13 o active-low dma request: when the internal control bit dmaen is set, the output dmareq* is asserted whenever internal fifo conditions warrant a dma transfer. dmareq* is deasserted on the falling edge of dmaack* when dma transfers must not continue past the current transfer.
october 1996 11 data book v2.0 pin information cl-cd1283 ieee 1284-compatible parallel interface controller dmaack* 12 i active-low dma acknowledge: this signal must never be asserted unless in response to a dmareq* from the device. dmaack* is the only bus handshake signal recognized during a dma transfer. (cs* must be high whenever dmaack* is asserted.) the direction of the dma transfer is determined by the internal control bit dmadir. svcreqp* 68 od active-low service request parallel: this is an open-drain output and must be tied to external v cc through a pull-up resistor. note that this output is only acti- vated by certain conditions on the parallel port (such as, negotiation changes, direction changes, etc.). svcreqp* is not activated by fifo threshold, or fifo full/empty con- ditions (refer to chapter 3 for information on how to use dmareq* to implement a fully interrupt-driven system). svcackp* 69 i active-low service acknowledge parallel: this input must not be driven active except in response to a parallel service request presented by the device. dgrant* 70 i active-low daisy grant: this input is driven active during service acknowledge cycles to enable the daisy-chain function. this input, when quali?d with ds* and a valid service acknowledge (svcackp*), activates the service acknowledge cycle. dpass* 71 o active-low daisy pass: this output is driven active during service acknowledge cycles to enable the next device in the daisy-chain. it is driven active when no valid ser- vice request exists and the service acknowledge input is active. in multiple cl-cd1283 designs, this signal is normally connected to the dgrant* input of the next device in the chain. pd[7:0] 41?8 i/o parallel port data lines [7:0]: bidirectional, depending on the protocol being used, these signals are used to transfer data over the interface between the master and slave. gp[7:0] 53?0 i/o general-purpose i/o [7:0]: general-purpose input/output port data lines. these signals are individually direction-programmable, acting as inputs or outputs. the direc- tion of each signal is controlled by the corresponding bit in the gpdir register. con- trol/status of the actual signals is provided through the gpio register. a_1284 31 i active-high 1284 active input: (slctin* in compatibility mode). ninit 34 i active-low init signal: (init* in compatibility mode). hstbsy 32 i active-high host busy signal: (autofd* in compatibility mode). hstclk 33 i active-low host clock signal: (strobe* in compatibility mode). note: the above four parallel handshake signals are driven by the master in an ieee std 1284 interface, and as such are inputs to the cl-cd1283. their functions depend on the transfer protocol selected. refer to the ieee std 1284-1994 document for protocol functions. (see chapter 8 for ordering information.) perclk 37 o active-low peripheral clock: (ack* in compatibility mode) perbsy 36 o active-high peripheral busy: (busy in compatibility mode) akdarq 35 o acknowledge data request: (perror* in compatibility mode) x?g 39 o extensibility flag: (select in compatibility mode) 1.3 pin descriptions (cont.) symbol pin no. type description
data book v2.0 october 1996 12 pin information cl-cd1283 ieee 1284-compatible parallel interface controller ndatav 38 o active-low data available signal: (fault* in compatibility mode) note: the above ?e parallel handshake signals are driven by the slave in an ieee std 1284 interface, and as such are outputs from the cl-cd1283. their functions depend on the transfer protocol selected. refer to the ieee std 1284-1994 document for protocol functions. (see section 3.4.1 on page 26 for ordering infor- mation.) ebdir 49 o external buffer direction: this signal is controlled by the internal parallel port control state machine and can be used to control the direction of an external buffer connected to the parallel port data bus. an external buffer might be desirable in appli- cations that require higher drive capacity than that provided by the cl-cd1283. ebdir can be used in conjunction with pdben to control this buffer. ebdir is a logic ? when the parallel data bus is in an output mode, and a logic ? when in an input mode. it can be connected directly to the direction control input of a 74245-type device. pdben 51 o parallel data bus enable: this signal can control a buffer on the parallel port data lines in applications requiring more signal-drive capability than provided by the cl-cd1283. pdben is controlled by the internal parallel port control state machine. when low, the parallel port data bus is not driving; when high, the port is in output mode and is actively driving. pdben will toggle between the on and off states during output modes and is only active (high) while the data bus pins are in the active driving state. pdben can be logically connected to the enable control of 74245 (or equivalent) bidirectional buffers (see section 3.9 and figure 3-10). 1.3 pin descriptions (cont.) symbol pin no. type description
october 1996 13 data book v2.0 register summary cl-cd1283 ieee 1284-compatible parallel interface controller 2. register summary local cpu communication with the cl-cd1283 occurs through a register set. within this register set, there are four types of registers: l global, common to all functions of the device l parallel pipeline l parallel port l service-acknowledge accessible global registers are always available to the cpu and their addresses are not affected by the con- tents of the aer (this register is provided to main- tain compatibility with the cl-cd1284) . note: aer must be set to ?0h and must not be changed (except to access rcr), or access to many registers will not work properly! the following tables de?e the register names, read and write access modes, internal address off- sets, and bit de?itions. a detailed description of each register, its contents and functions can be found in chapter 5 the address offset de?ed is the binary value that should be applied to the address inputs (a[6:0]) during i/o cycles. note that the addresses are shown relative to the cl-cd1283 de?ition of address lines. in 16- and 32-bit systems, it is a common practice to connect 8-bit peripherals to only one byte lane. thus, in 16- bit systems, the cl-cd1283 appears at every other address (for example, the cl-cd1283 a[0] input is connected to cpu a[1]). in 32-bit systems, the cl-cd1283 appears at every fourth address (cl-cd1283 a[0] is connected to cpu a[2]). in either of these cases, the address used by the pro- grammer will be different than what is shown in the tables. for instance, in a 16-bit motorola a 68000- based system, the cl-cd1283 is placed on data lines d[7:0], which are at odd addresses in the motorola scheme of addressing. the cl-cd1283 a[0] input is connected with a[1] of the 68000, a[1] with a[2], and so on. thus, the cl-cd1283 address 0x40 becomes 0x81 to the programmer. it is left-shifted one bit and a[0] must be ? for low- byte (d[7:0]) accesses. 2.1 register summary tables table 2-1. global registers name hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page aer 68 poll poll poll poll poll 0 0 0 44 gfrcr 4f firmware revision code 44 gpdir 71 dir 7 dir 6 dir 5 dir 4 dir 3 dir 2 dir 1 dir 0 45 gpio 70 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 45 pir 61 ppireq pport pipeline 0000046 ppr 7e binary value 46 svrr 67 dmareq n/u n/u n/u srp n/u n/u n/u 47
data book v2.0 october 1996 14 register summary cl-cd1283 ieee 1284-compatible parallel interface controller a ? indicates ?on? care? table 2-2. virtual registers name hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page eosrr 60 x a xxxxxxx48 pivr 40 xxxxxit2it1it049 table 2-3. parallel pipeline registers name hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page der 33 dmawrerr dmarderr bufwrerr bufrderr hr1wrerr hr1rderr hr2wrerr hr2rderr 50 dmabuf (high byte) 30 15 14 13 12 11 10 9 8 51 dmabuf (low byte) 30 7 6 5 4 3 2 1 0 51 hrsr 34 hr1full hr1tag hr2full hr2tag dmafull dmaempty dmaact ctnot0 52 htvr 24 htvr[7] htvr[6] htvr[5] htvr[4] htvr[3] htvr[2] htvr[1] htvr[0] 53 livr 18 user-de?ed bits it2 it1 it0 54 pacr 3f shrtten shrtstal staleoff fifolock clearto 0 asyncdma 0 55 pcrr 6c 0 0 0 0 0 0 0 pchreset 56 pfcr 31 fifores dmaen dmadir inten rleen settag erren dmabufwe 56 pfep 39 0 0 6-bit binary fifo pointer value 57 pffp 38 0 0 6-bit binary fifo pointer value 57 pfhr1 35 8-bit character data 58 pfhr2 36 8-bit character data 58 pfqr 3a data or space available in fifo ?max 0x40 58 pfsr 32 fffull ffempty timeout hrtag hrdata stale onechar dataerr 59 pftr 3b 0 dma transfer threshold 60 rlcr 37 0 7-bit unsigned binary count 60 sdtcr 3d 8-bit stale data timer count 61 sdtpr 3c 8-bit stale data timeout value 61
october 1996 15 data book v2.0 register summary cl-cd1283 ieee 1284-compatible parallel interface controller table 2-4. parallel port registers name hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page ear 25 8-bit binary value 62 ivr 2e 0 0 0 0 a1284 ninit hstbsy hstclk 62 mdr 21 8-bit binary data 62 ner 28 0 rid 0 epp rle ecp rvb rvn 63 nsr 29 negok negfl hostto invalid 4-bit negotiation result code 64 odr 2d 0 0 0 0 a1284 ninit hstbsy hstclk 65 ovr 2b perbsy perclk akdarq xflag ndatav 0 0 0 65 pcier 22 0 0 negch sigch eppaw dirch idreq ninit 66 pcisr 23 0 0 negch sigch eppaw dirch idreq ninit 66 pcr 20 manmd e1284 etxfr ig_sel htmrtst[1] htmrtst[0] mmdir manoe 67 scr 2a 0 0 0 0 clrps setps epirq revrq 68 spr 26 8-bit binary value 69 ssr 2f 0 0 0 0 a1284 ninit hstbsy hstclk 70 zdr 2c 0 0 0 0 a1284 ninit hstbsy hstclk 70 table 2-5. special register name hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page rcr 051000000170
data book v2.0 october 1996 16 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3. functional description 3.1 device architecture the cl-cd1283 consists of dedicated logic tailored to the function of sending and receiving parallel data. the device implements an ieee 1284-compli- ant parallel port with a specialized data pipeline designed for high-speed transfers. to maintain binary compatibility with the cl-cd1284, much of the architectural layout has been duplicated. therefore, access to the register set of the parallel channel is only possible after load- ing the aer with the cl-cd1284 occupied parallel port address ?namely channel 0. for all channel- speci? accesses, the cpu ?st loads the aer with a pointer to channel 0. thereafter, all read and write operations occur through the parallel channel. the parallel channel is comprised of a fifo and dma data interface, as well as a high-speed state machine to manage all modes de?ed in the ieee std 1284-1994 speci?ation, standard signaling method for a bidirectional parallel peripheral inter- face for personal computers . the parallel port per- forms the slave or peripheral function of the ieee std 1284 interface, and can accept negotiations into any or all of the ieee de?ed modes. 3.2 cpu interface the cpu interface is comprised of a 7-bit address bus, 8-bit bidirectional data bus, 16-bit dma port, and control inputs to identify the type of i/o cycle occurring. the signaling and basic timing match that of the motorola a 68000 family. with the addition of minimal glue logic, the interface will work with nearly any cpu. a special input is provided to swap the bytes on the data bus to reduce the necessary logic needed with intel a -style cpus. the interface is completely compatible with the cl-cd1284. therefore, a cl-cd1283 can be inserted into a system in instead of a cl-cd1284 and the parallel port operates without any modi?a- tions to the cpu interface, parallel port hardware or software. in most cases, when the cpu reads or writes an internal cl-cd1283 location, it accesses a location in a ram array to serve as a bank of registers. how- ever, some locations are mapped to actual hard- ware resources. for example, when a hard output signal is required (such as a service-request output figure 3-1. functional block diagram bus interface and dma logic parallel port fifo parallel port logic control state machine interrupt logic registers pipeline pipeline control
october 1996 17 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-2. internal address generation cpu address address generation aer ram register array parallel port registers in the svrr) or a read of the actual state of an input is necessary (such as a parallel port handshake sig- nal in the ivr). the cl-cd1283 is a synchronous device. all inter- nal operations occur on edges and levels (phases) of the internal clock. the internal clock is generated by dividing the external (system) clock by two. when the cpu performs an i/o cycle with the cl-cd1283, it strobes; address and data are sampled on the ris- ing edges of the internal clock. as illustrated in chapter 6, external control signals must meet setup times with respect to system clock edges. once a cycle starts, the sequence of events is locked to the cl-cd1283 clock, with events (address setup, write data setup, and read data available) occurring at predictable times. it is not necessary to design a synchronous inter- face to the cl-cd1283. in an asynchronous design, the dtack* (data transfer acknowledge) signal indicates that the cl-cd1283 has com- pleted the requested data transfer for all i/o cycles except dma. dtack* can be an input to wait-state generation logic that pauses the cpu until the operation is complete. if the cs* and ds* strobes (chip select and data strobe) do not meet the minimum setup time with respect to the system clock edge, the cl-cd1283 does not detect the i/o request, and the cycle delays for two full-sys- tem clock cycles, meeting the setup time. the i/o cycle commences and follows the predictable timing with dtack* signaling the end. 3.2.1 read cycles read cycles are initiated when both the cs* and ds* inputs are activated and the r/w* (read/write) input is high. all strobes and address inputs must meet the setup times as speci?d in chapter 6. both the cs* and ds* signals must be valid for a cycle to start. cycle times are measured from whichever of the two signals goes active last. the cl-cd1283 signals the completion of the read cycle (placing the data from the addressed register on the data bus pins) by activating dtack*. the read cycle termi- nates when the cpu removes cs* and ds*. 3.2.2 write cycles write cycle timing and strobe activity is nearly iden- tical to read cycles except that the r/w* signal must be held low. write data, strobes, and address inputs must meet setup and hold times as speci?d in chapter 6. dtack* indicates that the cycle is com- plete and the cl-cd1283 has accepted the data. removing both cs* and ds* terminates the cycle. 3.2.3 service-acknowledge cycles service-acknowledge cycles are a special-case read cycle. timing is basically the same as a normal read cycle, but the svcackp* input is activated
data book v2.0 october 1996 18 functional description cl-cd1283 ieee 1284-compatible parallel interface controller instead of the cs* input (a slightly longer setup time is required on the svcackp* input than on the cs* input). the data that the cl-cd1283 provides dur- ing the read cycle is the contents of the pivr. as with read and write cycles, dtack* indicates the end of the cycle and removing ds* and svcack* terminates the cycle. note: with regard to timing and service-acknowledge cycles, when the cpu completes the service routine and writes to the eosrr, a subsequent i/o cycle, if started immediately, is delayed approximately 1 m s by delaying dtack*. this is due to the time required by the internal proces- sor to complete activities associated with the service-acknowledge cycle. these activities are primarily interrupt-logic updates and restoration of the environment prior to the service-request/service-acknowledge proce- dure. these must be completed before any internal registers are modi?d by the cpu. if the cpu attempts an access before the internal procedures are complete, the cl-cd1283 will hold off the cycle until it is ready. in system designs that monitor dtack*, this is not a problem; the cycle is extended until dtack* becomes active, and the delay is automatically met. if a system design does not monitor dtack*, a mechanism must be pro- vided to introduce the required delay. s warning: failure to observe the above delay requirement can cause device mal- function. 3.2.4 dma cycles the cl-cd1283 provides a bidirectional, 16-bit dma interface to the parallel port. this is the only direct-data interface to the port; other 8-bit register accesses make use of the normal cpu interface, as previously described. the handshake between the cl-cd1283 and the dma circuitry uses two signals: dmareq* and dmaack*. the address bus is ignored during dma transfers. when internal conditions warrant a dma transfer (as when the fifo falls below the pro- grammed threshold in the forward direction or rises above the threshold in the reverse direction) and dma transfers are enabled through the pfcr, the device requests dma service by driving dmareq* low. dmareq* remains active until the fifo has less than two empty byte locations remaining (for- ward direction) or until the fifo has less than 2 bytes remaining (reverse direction). in the forward direction, the dma controller logic responds by plac- ing data on the 16-bit data bus and driving the dmaack* input low. this cycle is repeated until the fifo has less than two empty byte locations remaining or there is no more data to send. in the reverse direction, the cl-cd1283 responds to the active dmaack* signal by driving the contents of the dmabuf register onto the data bus. odd-byte transfers in the reverse direction are han- dled on an interrupt basis. when the number of bytes in the fifo is odd, all bytes except the last are transferred through a number of 16-bit dma cycles (two bytes per cycle). the odd byte remaining is held in pfhr1 and an interrupt generated when the stale data timer expires. status indicating that pfhr1 contains data is indicated in the pfsr. the cpu interrupt service routine must manually remove the remaining byte from the interface. in the forward direction, an odd remaining byte can be directly writ- ten to the pfhr1 once the last dma cycle is com- plete. one additional input signal determines the endian format (whether the least-signi?ant byte is on data bits 7:0 or 15:8) of the 16-bit dma buffer. byteswap selects whether the lower or upper byte of the dma buffer moves into the fifo data pipeline ?st in the forward direction, or from the fifo data pipeline to the dma buffer ?st in the reverse direction. if byteswap is low, then the least-signi?ant byte (db[7:0]) immediately moves into or out of the data pipeline. if byteswap is high, the opposite occurs (db[15:8] move into or out of the pipeline ?st). the effective duration of the dma transfer block (burst) is determined by the threshold value in the pftr. regardless of where the port is moving data when this threshold is reached (exceeded in receive; less than in transmit), a dma cycle begins and remains active until the fifo has less than 2 bytes remaining (receive) or has less than two empty byte locations remaining (transmit). the svrr provides can determine if a dma cycle is being requested. svrr[7] is true if a dma cycle is
october 1996 19 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller currently being requested. this status indication is provided as a general system status. refer to chapter 6 for detailed information on dma cycle options and timing values. 3.2.5 interrupts the term interrupt is a generalized description of the method where the cl-cd1283 gains the attention of the cpu. interrupt is used interchangeably with ?ervice request as the two are the same function. interrupt often describes an unconditional response on the part of the cpu. whether or not this is the case, the source is still the same ?a service request from the cl-cd1283. the hardware signal generated by the cl-cd1283 (svcreqp*) can be connected to the cpu interrupt input to start an interrupt service routine. the service routine can then begin servicing the request from the cl-cd1283 by starting an acknowledge sequence. 3.2.6 dmareq* as interrupt source interrupts are not generated by fifo threshold con- ditions; therefore, if the system design requires data to move through interrupts, connect dmareq* directly to a cpu interrupt input or logically or it into the same cpu interrupt input as svcreqp*. if dmareq* is used to generate interrupts, the follow- ing are required: 1) a 16-bit data interface must be implemented to support 16-bit reads of the dmabuf register. 2) the dma threshold value in the pftr must be initialized. 3) the dmareq* remains active until the fifo is nearly empty (rx) or nearly full (tx), followed by the toggling of dmaen if data is moved to/from the fifo through pio (refer to section 3.2.4). however, the software can easily change this by clearing the dmaen bit (pfcr[6]) at the start of the interrupt service routine and setting it again at the end. 4) if svcreqp* and dmareq* are logically or?d together, the service routine must start by checking the svrr to determine which signal is active. 5) svcackp* must not be activated in response to dmareq*; likewise, dmaack* must not be activated in response to svcreq*. 6) the dmadir bit (pfcr[5]) can determine whether to write or read to/from the dmabuf register. 7) the pfqr can determine how many reads of the 16-bit dmabuf register are necessary to empty the pipeline. note however, four must be added to the pfqr value, then that number then must be divided by two and truncated to the nearest integer (this accounts for the extra four bytes in the two holding registers and the 16-bit dmabuf register, as well as 16-bit instead of 8- bit reads). 3.2.7 daisy-chain con?urations multiple cl-cd1283s can be connected in a daisy- chain con?uration, forming systems with multiple parallel ports. the device provides all signals neces- sary for this con?uration, with only minimal external logic being (see figure 3-3). when the cpu acknowledges the request, both cl-cd1283s receive the acknowledge through svcack*. however, only the device receives dgrant*. if it has an active request of this type pending, it takes the acknowledge and drives the vector register (rivr, tivr, mivr) onto the data bus. if the ?st device does not have a request pending, it passes dgrant* to the second cl-cd1283 through dpass*. assuming that the second cl-cd1283 has an active request pending, it then takes the acknowledge and drives its vector register onto the data bus.
data book v2.0 october 1996 20 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-3. cl-cd1283 daisy-chain con?uration dpass* dgrant* dpass* dgrant* svcackp* svcackp* svcreqp* svcreqp* address decode logic cycle error cl-cd1283 cl-cd1283 as previously mentioned, the upper 5 bits of the livr re?ct what the cpu loaded into them during initialization of the cl-cd1283s. these bits are used as a unique chip identi?ation number. now the cpu can determine which cl-cd1283 responded to the service acknowledge. these ?e bits could be set to binary ? in the livrs of the ?st cl-cd1283, and to binary ?0001 in those of the second. the cpu is able to test the bits to determine which device responded. some exam- ples of service-acknowledge software routines that show one way of performing this task are provided in chapter 4. caution: if no cl-cd1283 in the chain has a pend- ing request, dgrant* is passed by the last cl-cd1283 and none respond. this causes the bus cycle to fail (no dtack* is generated). the only time this happens is when an error condition outside the cl-cd1283 s cause the cpu to respond to a request that is not made. provide a mechanism to terminate or abort the bus cycle if this error occurs. this can be accomplished with timeout circuitry, or the dpass* output of the last cl-cd1283 can activate an abort condition. other devices, such as the cl-cd1400, can share the daisy-chain mechanism and be connected to the dpass* output of the last cl-cd1283 in the chain. the actual implementation is system-dependent, but it is important to provide some way for the cpu to determine that the cycle did not complete normally if no device responds to the acknowledge cycle.
october 1996 21 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.3 parallel port service requests service requests can derive from two internal sources: the data pipeline or the parallel port state machine (see figure 3-4 on page 22). if the data pipeline internal service request becomes active, the pipeline bit (pir[5]) is set; likewise, if the parallel port state machine internal service request becomes active, the pport bit (pir[6]) is set. internal service requests from these sources are monitored through the pipeline and pport bits by microcode running in the internal mpu. when either (or both) of these bits are detected active, the microcode sets the ppireq bit (pir[7]). the ppireq bit is also mir- rored by the srp bit (svrr[3]). the svrr is useful in polled systems because it allows the detection of dma service requests, as well as parallel port ser- vice requests with a single register read operation. note: for speci? register de?itions and default set- tings, refer to chapter 5. both internal sources of service requests within the parallel channel have their own enable functions. interrupts from the data pipeline are enabled through the pfcr; interrupts from the parallel port state machine are enabled through the pcier. the pfcr has two enable bits: one for normal inter- rupts (such as tagged data being received), and one for data errors (such as a cpu write to a holding reg- ister that already holds data). the ?st type of inter- rupt is enabled through the inten bit (pfcr[4]). the second type of interrupt is enabled through the erren bit (pfcr[1]). note that inten must be set for erren to generate an interrupt; however, the cpu need not enable error interrupts if it does not require noti?ation of these types of errors. the error inter- rupt is generated if the dataerr bit (pfsr[0]) is a non-zero. in this case, the der indicates the cause of the error interrupt. the parallel channel-control state machine can generate six types of interrupts. each of these has its own enable bit in the pcier: l negch for negotiation changes l sigch for signal changes on the port status inputs (manual mode only) l eppaw for epp protocol address writes l dirch for direction changes on the parallel chan- nel l idreq for slave id requests from the remote master. l ninit for initialization pulses from the master (compatibility mode only) any or all of these bits may be set, based on the mode of operation. the negch interrupt is issued whenever the remote master performs a protocol change, such as moving from compatibility mode to ecp; the cpu examines the nsr to determine the new state of the parallel interface. signal changes can be identi?d by reading the ssr. in response to the eppaw interrupt, the cpu would read the ear to retrieve the value that was written during the epp address write cycle.
data book v2.0 october 1996 22 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-4. interrupt generation logic failed neg. (invalid extcode) [compatibility mode] nsr=0x41 termination [compatibility mode] nsr=0x82 neg-ok nsr=0x86[epp mode] {40} nsr=0x88[rn mode] {00} nsr=0x8a[rb mode] {01} nsr=0x8c[ecp w/o rle] {10} nsr=0x8e[ecp w/ rle] {30} neg-ok nsr=0x89[rn id request] {04} nsr=0x8b[rb id request] {05} nsr=0x8d[ecp w/o rle id request] {14} nsr=0x8f[ecp w/ rle id request] {34} idreq pcisr[1] negch pcisr[5] idreq pcier[1] negch pcier[5] failed neg mode not enabled [compatibility mode] nsr=0x46 (epp) nsr=0x48 (rn) nsr=0x49 (rn-id) nsr=0x4a (rb) nsr=0x4b (rb-id) nsr=0x4c (ecp) nsr=0x4d (ecp-id) nsr=0x4e (ecp-rle) nsr=0x4f (ecp-rle-id) host timeout host has not responded for over 1 sec.) [compatibility mode] nsr=0x22 invalid host has violated handshaking sequence [compatibility mode] nsr=0x16 (epp) nsr=0x18 (rn) nsr=0x19 (rn-id) nsr=0x1a (rb) nsr=0x1b (rb-id) nsr=0x1c (ecp) nsr=0x1d (ecp-id) nsr=0x1e (ecp-rle) nsr=0x1f (ecp-rle-id) note: an immediate termination from the host generates this interrupt note: id requests fail if either the negotiation type or rid is disabled in ner. other negotiations also fail if the negotiation type is disabled. key: [ ] = current mode { } = interface extensibility request value (see ieee1284 std for more details) (register name[x]) : x = bit #, that is pcier[1] = pcier, bit 1 a1284 signal transition from low-to-high, and a1284(odr[3]) = 1 ninit signal transition from low-to-high, and ninit(odr[2]) = 1 hstbsy signal transition from low-to-high, and hstbsy(odr[1]) = 1 hstclk signal transition from low-to-high, and hstclk(odr[0]) = 1 manmd (pcr[7]) sigch (pcier[4]) sigch (pcisr[4]) note: interface must be in compatibility mode when manmd (pcr[7]) is set or manmd has no affect hstclk signal transition from high-to-low, and hstclk(zdr[0]) = 1 hstbsy signal transition from high-to-low, and hstbsy(zdr[1]) = 1 a1284 signal transition from high-to-low, and a1284(zdr[3]) = 1 ninit signal transition from high to low, and ninit(zdr[2]) = 1 host has reversed the direction of the interface from ecp-forward to ecp- reverse by driving nreverserequest (ninit) signal low. host has changed the direction of the interface from ecp-reverse to ecp-for- ward by driving nreverserequest (ninit) signal high. dirch (pcisr[2]) eppaw (pcisr[3]) ninit (pcisr[0]) eppaw (pcier[3]) epp address received on parallel port ninit (pcier[0]) in compatibility mode, the host has requested the peripheral to re-initialize itself (ninit went low). inten (pfcr[4]) pport (pir[6]) (pcisr[5]) negch (pcisr[4]) sigch (pcisr[3]) eppaw (pcisr[2]) dirch (pcisr[1]) idreq (pcisr[0]) ninit
october 1996 23 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-4. interrupt generation logic (cont.) dataerr (pfsr[0]) ppireq (pir[7]) inten (pfcr[4]) pipeline (pir[5]) onechar (pfsr[1]) timeout (pfsr[5]) interface in forward direction, pfhr2 full, pfhr1 empty, and timeout (pfsr[5]) is set. stale (pfsr[3]) is set and, if interface is in forward direc- tion, the fifo is empty. onechar (pfsr[1]) timeout (pfsr[5]) pport (pir[6]) pipeline (pir[5]) srp (svrr[3]) erren (pfcr[1]) dataerr (pfsr[0]) dmawrerr (der[7]) (dmaack* w/o dmareq*) dmarderr (der[6]) (dmaack* w/o dmareq*) bufwrerr (der[5]) (write to non-empty dmabuf) bufrderr (der[4]) (read from empty dmabuf) hr1wrerr (der[3]) (write to non-empty hr1) hr1rderr (der[2]) (read from empty hr1)) hr2wrerr (der[1]) (write to non-empty hr2) hr2rderr (der[0]) (read from empty hr2)
data book v2.0 october 1996 24 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-5. control signal generation dgrant* cl-cd1283 cs* r/w* ds* ad[6:0] db[7:0] svcackp* cpu address cpu i/o control address decode logic cpu data a direction change (dirch) interrupt occurs when the remote master has reversed the interface from ecp forward to ecp reverse or ecp reverse to ecp forward. the idreq interrupt is generated when the remote master issues an id request command dur- ing ieee 1284 negotiations. the normal response by the local cpu is to send its id string after revers- ing the direction of the data pipeline by setting the dmadir bit to ?? if vectored interrupts are required by the system, then the livr must be initialized by the local cpu. the upper ?e bits are de?ed by the local cpu and can be any value appropriate to the system design. the lower three bits should be initialized to zero dur- ing the programming of the livr, however they are ?on? cares and masked in the pivr to provide the vector indicating the source, and type of request from the parallel channel. access to the parallel channel livr is made by ?st setting the aer to ??0? making the channel zero register set accessible. since the livr is a read/write register, the local cpu can read it at any time. when read during a normal read cycle, the upper 5 bits return the original value loaded by the cpu. the three least-signi?ant bits always ready back as the current service-request status of the parallel port if an interrupt is in progress; otherwise they read back as ?? the encoding of the three least-sig- ni?ant bits of livr during a service acknowledge cycle indicates which of the functional blocks in the parallel channel is requesting service as shown in the following table. table 3-1. livr[2:0] encoding it2 it1 it0 requestor 100 channel control state machine 1 0 1 data pipeline 1 1 0 both
october 1996 25 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.3.1 hardware-activated acknowledge when conditions within the parallel channel require attention, a request is made through the svcreqp* output. if the system is interrupt driven, this output is connected to the cpu interrupt-gener- ation circuitry. in a hardware-activated service- acknowledge system, the cpu responds to the request by activating the svcackp* input along with dgrant* and ds*; the cs* input is not used and must remain inactive (high). the cl-cd1283 responds to the svcackp* cycle by driving the contents of the pivr onto the data bus with it2?t0 encoded as shown in table 3-1. the svcackp* cycle also places the device in the correct context to service the parallel channel request. the vector supplied by the pivr indicates which block of the parallel channel requested service; the cause of the request is indicated in the status request registers of each; the pcisr in the channel control state machine block and/or the pfsr in the data pipeline block. the i/o cycle that activates the svcackp* input also removes the active svcreqp* output. the request output remains inactive until after the cpu terminates the acknowledge routine by a write to the eosrr. this is a dummy operation and the data written is ?on? care? the purpose of the write is to clear the internal logic of the current request context and allow it to generate another request when required. until this write occurs, no further service requests can be made from the parallel channel. when the mpu detects the write to the eosrr, it clears the pivr bits to ? in preparation for the next service-request cycle. 3.3.2 software-activated acknowledge during a normal read cycle, the livr always reads back with the lower 3 bits, indicating the current ser- vice-request status of the device. thus, in a poll- mode system, this register can be used in conjunc- tion with the svrr to determine if service request needs are pending and, if so, which of the two pos- sible sources is active. if the srp bit is set (svrr[3]), at least one of the request conditions is true and a subsequent read of the livr indicates the source. a scan of just the svrr allows the poll- ing routine to perform only one read cycle to deter- mine if a parallel request is pending. if the svrr indicates an active parallel channel service request, the software can initiate the appropriate service rou- tine that reads pir to determine the source of the parallel port request. the pport and pipeline bits indicate the block requesting service. once the cpu satis?s the request needs of the parallel channel, it must toggle the inten bit (pfcr[4]) or clear the pir. toggling inten clears the ppireq, pport, and pipeline bits (pir[7:5]). this action also informs the mpu to clear the pivr and remove the external request. the ppireq bit can be cleared at any time by the cpu once it enters the service routine. if the system design requires that the request be removed quickly, this procedure can be performed at the beginning of the polled service routine. after the interrupt source is determined, the cpu can clear pir or toggle inten, then the pir is automatically cleared. 3.4 parallel port fifo and data pipeline the parallel port within the cl-cd1283 implements all modes de?ed for the ?lave (peripheral) side of the ieee std 1284 standard signaling method for a bidirectional parallel peripheral interface for per- sonal computers . this speci?ation de?es four methods of performing bidirectional data transfers between a computer system and a peripheral device, in addition to the generally accepted unidi- rectional centronics a -compatible mode. these modes include compatibility mode, reverse-nibble mode, reverse-byte mode, ecp (extended capa- bilities port) with and without rle (run-length encoding, and the epp (enhanced parallel port). the ieee 1284-compliant parallel port consists of two major functional blocks: l a data pipeline that moves data between the parallel port and the cpu and includes a fifo, holding registers, dma control, and interrupt control logic. l a channel control state machine to performs all control and handshake generation on the paral- lel port interface side of the device.
data book v2.0 october 1996 26 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.4.1 ieee standard 1284 protocols the following sections discuss data movement within the pipeline for the various ieee std 1284 operating modes. for a complete description of these modes, refer to the ieee std 1284 speci?a- tion; it is beyond the scope of this data book to relate complete information on the speci?ation. a copy of the ieee std 1284-1994 can be obtained from: ieee standards department 445 hoes lane p.o. box 1331 piscataway, nj 08855-1331 usa 3.4.2 bus interface dma transfers are the preferred means of transfer- ring data to/from the fifo. however, it is also possi- ble to transfer data to/from the data pipeline by reading and writing the holding registers directly through pio. dma request and acknowledge hand- shake signals support transfers to/from the 16-bit- wide dmabuf register. the direction of transfer is determined by the dmadir bit (pfcr[5]). in the transmit direction, with dmabufwe set (pfcr[0]), the cpu can write 2 bytes at a time directly to the dmabuf register. however, most applications are not concerned with speed on the parallel port in the reverse direction and do not require 16-bit writes to the fifo. the cpu must avoid writing to these registers when they are already full or reading from them if they are empty. the status bits in the hrsr indicate if the holding registers and the dma buffer are full or empty. when writing a block of data to the cl-cd1283 (with dmabufwe set to ??, the cpu can determine how much data the fifo can accommodate by reading the pfqr. should data become ?rapped in the dmabuf register in the receive direction because of a failure of the external dma controller or because the exter- nal buffer area is full, it can either remain until the dma transfer can be resumed or the cpu can read the data directly from the dma buffer. note: the dma buffer can only be read when dmareq* is active because data is not moved into the dmabuf register until dmareq* is activated by the threshold logic or a timeout condition. once a dma request is initiated by the cl-cd1283, it is maintained until the last data transfer the fifo can accommodate occurs, or the cpu either clears dmaen or clears the fifo and data-transfer logic by setting fifores. in the transmit direction, the dma request is removed by the cl-cd1283 when it determines that the fifo is nearly full. (if rleen is set, the pipeline does not fully drain into the fifo, but the logic does not factor that into the decision to conclude the dma transfer.) in the receive direction, the dma request is removed when there are not at least two more bytes available to transfer or a tagged byte has moved into the data pipeline. in the latter case, an interrupt is generated to the cpu (inten must be true) to remove the tagged data from the pipeline. the quantity of data transferred within a single dma request can signi?antly exceed the capacity of the fifo if rleen is set, the parallel port is in ecp mode, and compressed data is being transferred. this is because the fifo always stores the data in compressed form. since other modes do not sup- port rle compression, the cpu should only set rleen when the parallel port interface is in ecp mode. 3.4.3 parallel port fifo the cl-cd1283 has a dedicated 64-byte fifo with counters to maintain the ?l/empty pointer addresses, logic to manage data transfers, auto- matic dma handshake, and status interrupts to the cpu. a simple register interface provides control over setting the direction of the pipeline, initializ- ing/resetting the dma pointers, setting the dma threshold, and so on. the fifo management logic responds to data-transfer requests from the dedi- cated ieee 1284 parallel port state machine. byte-alignment issues on transfers to/from the fifo are avoided by having the fifo byte-oriented with 2-byte word packing/unpacking occurring between the dmabuf register and pfhr1 and pfhr2. the order of byte transfers to/from the dma buffer is con- trolled by the byteswap input. if byteswap is high, the upper byte (bits 15:8) transfers ?st. if
october 1996 27 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller byteswap is low, the lower byte (bits 7:0) trans- fers ?st. data transfers to/from the cpu are initiated by a dma request whenever the quantity of data or space in the fifo equals or exceeds the threshold value stored in the pftr. the dma request is deas- serted during the dma cycle determined by the logic to be the last because of ?ling/emptying the fifo or the presence of tagged data in the receive pipeline. 3.4.4 receive direction in the receive direction (dmadir = 0), the ?st two bytes of data placed into the fifo by the parallel port are immediately moved into the data pipeline, pfhr1 and pfhr2 (see figure 3-6 on page 29). this is done in part to make the tagged status of the data visible to the pipeline control logic. if rleen is ?? any tagged data from the fifo must move through the pipeline. however, tagged data cannot be transferred to the cpu by a dma transfer from the dmabuf register. therefore, the presence of tagged data in the pipeline causes an interrupt to the cpu. the cpu must then examine the hrsr to determine the pipeline status. if there is tagged data in one of the holding registers, the cpu must read that register to empty it and clear the tag. if more data is available in the fifo, data immediately moves forward to ?l the pipeline. if the fifo is empty, the pipeline does not move so, if the cpu emptied pfhr2 and pfhr1 is full, the data in pfhr1 moves forward to pfhr2 only if the fifo is not empty. the pipeline logic keeps the pipeline full in the receive direction. the value in the threshold register is tested against the quantity of data in the fifo. therefore, a number of characters equal to the pftr-threshold value plus two must arrive before a dma request is made to the cpu to remove the data. 3.4.5 receiving compressed data rle compressed data sequences that consist of a tagged rle count followed by the compressed data character, are stored in the fifo in compressed form. as data is moved from the fifo into the data pipeline, the tag bit is inspected. if the tagged data is an rle count (hostack signal is high) and rleen is true, the rle count is loaded into the rlcr instead of pfhr1; the next data character is loaded into pfhr1. decompression occurs by holding the compressed character in pfhr1 as copies of the character are shifted forward into pfhr2. as each copy of the character is shifted, the rlcr value decrements. when the rlcr has reached zero, the hold on pfhr1 is released and it can shift forward in the pipeline as ordinary data. tagged data from the fifo is recognized to be an ecp mode address and shifts into the pipeline where it causes an interrupt to the cpu to remove the tagged data from the pipeline. if rleen is ?? all tagged data from the fifo is shifted into the pipeline and produces cpu interrupts. if an immediate termination occurs between the reception of the rle count and the corresponding data, then the rle count is stored in rlcr and the next data byte received in ecp mode is uncom- pressed into the fifo (based on the values in rlcr provided and if rleen is still set). if the next byte received in ecp mode is a new rle count, then that value overwrites the old value in the rlcr. 3.4.6 stale data (stale, onechar, and timeout status bits) data transfers to the cpu can also be initiated by the stale data timer. this timer is reloaded with the value in the sdtpr and restarts each time data is placed into the fifo from the parallel port. when the timer reaches zero, the status indication stale bit (pfsr[2]) is set true unless staleoff (pacr[5]) is true. staleoff keeps the stale status bit false, even though the sdtcr counter value is zero. should the stale status become true with at least two characters of data available, a dma request is made to transfer the data. if the stale status is true and there is exactly one character available, the onechar status bit (pfsr[1]) is set and an interrupt generated to the cpu to transfer the single residual character. the pfsr indicates the stale, onechar, and ffempty conditions. the hrsr shows that pfhr2 contains the ?al character. an odd number of bytes cannot be transferred by dma. if a dma transfer completes with one byte of data remaining, the data
data book v2.0 october 1996 28 functional description cl-cd1283 ieee 1284-compatible parallel interface controller is held pending arrival of additional data or the expi- ration of the stale data timer. the onechar status is latched true when the fifo and the dma buffer are empty, and there is one character in the pipeline in pfhr2. while the one- char status is true, further pipeline operations are inhibited. if additional data arrives in the fifo, it remains there until the cpu: 1) services the interrupt caused by the onechar status, and 2) reads the data character from pfhr2. if new data has arrived since the onechar status bit was latched, the ffempty bit will be false. when the cpu reads the single character from pfhr2, any newly arrived data in the fifo immediately moves forward into the pipeline and a dma transfer can begin if conditions warrant. another latched status condition associated with the stale data timer is the timeout status bit (pfsr[5]). timeout is reset by the fifores bit (pfcr[7]) and the clrto bit (pacr[3]). timeout, onechar, and dataerr are pipeline interrupt conditions and, if enabled, generate an interrupt. in the receive direc- tion, the timeout condition is armed when stale is ? and clrto and fifores are also ?? when stale becomes ?? the timeout is triggered, but not set until any dma transfer is complete, the fifo is empty, and there is no more than one character left in the pipeline. to clear the timeout condition, set the clrto bit. to reenable the timeout function, clear clrto. the cpu can arm the timeout by a write of ?1h directly to the sdtcr. if the timer expires before any data arrives, an interrupt is generated for the timeout condition. if data arrives before the timer expires, the interrupt delays until the data becomes stale. 3.4.7 transmit direction note: in the transmit direction, the pipeline behaves in one of two ways depending on the state of the rleen control bit. rleen should only be set by the cpu after the parallel port is in ecp mode, otherwise compression of data occurs, but can- not be supported in data transfers on the paral- lel port. if rleen is ?, data written to the dmabuf register by a dma (dmaen true) or cpu write (dmabufwe true) will be moved through pfhr1 to pfhr2 and immediately transferred into the fifo (if space is available). if rleen is ?, run-length encoding is enabled and comparators among the pipeline stages recognize repeated strings of characters and compress them (see figure 3-7 on page 30). to allow the compara- tor-based logic to work, the pipeline registers, pfhr1 and pfhr2, must be kept full. one compar- ator determines if the characters in pfhr1 and pfhr2 are identical. another comparator determines if the next charac- ter coming from the dmabuf register and the char- acter in pfhr1 are identical. compression begins when the pipeline is full (immediately after a dma or cpu write to the dma buffer) and both comparators show identical characters in their pipeline stages. this starts the compression process and the char- acter in pfhr1 and the character in the dma buffer are shifted forward. the (same) character in pfhr2 is not loaded into the fifo, but rather the rlcr is increments to ?. as long as identical additional characters are loaded into the dma buffer, the rlcr value continues to increment and the data in pfhr2 is not moved into the fifo. when the repeated sequence is ?ally broken or the rlcr count reaches 127, the rlcr value transfers into the fifo, the rlcr zeroes, and the character in pfhr2 transfers into the fifo. compression resumes when both comparators again indicate the presence of a string of at least three identical char- acters. during intervals between dma transfers, the last two data characters are held in pfhr1 and pfhr2. after the entire block transfer is complete, the cpu must either force rleen to ? or ensure that both dmaen and dmabufwe are ?? when either of these conditions is true, the pipeline is released and the data held in pfhr1 and pfhr2 transfers into the fifo. the timeout interrupt can be used as a general timer interrupt in the transmit direction. unlike the receive scenario, when dmadir is true, the timeout status bit is immediately set when the timeout is triggered by a ??to-? transition of stale. to use the timeout interrupt, the cpu must load the desired time delay directly into the sdtcr. when the timer expires,
october 1996 29 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller stale becomes true and the timeout interrupt is acti- vated. 3.5 parallel port overview 3.5.1 terminology this document uses the terms ?aster and ?lave for the ieee-1284-speci?ation terms ?ost and ?eripheral? which describe the two sides of a par- allel port interface. 3.5.2 signal names the ieee-1284 speci?ation uses different names for the nine control signals, depending on the cur- rent mode of operation (see table 3-1 on page 24). the cl-cd1283 uses ?ed names for each of the pins. the names were selected to represent the most commonly used names amongst the various protocols. the cl-cd1283 device operates as a slave only. there are four input-control signals driven by the master-side device, and ?e output- control signals driven by the slave-side device. the parallel data bus (pd[7:0]) is bidirectional. 3.5.3 state machine the parallel port is controlled by a large synchro- nous state machine. the state machine is based on the ieee std 1284-1994 and conforms to all the functional modes (except extensibility link options, which are not currently de?ed, as of the print date of this document). 3.5.4 con?uration at power-up, the interface begins in compatibility mode (centronics mode) ready to accept data from the master. only the etxfr bit (pcr[5]) is required to allow transfers in compatibility mode. pcr[7:5] enable transfers, negotiations, and man- ual mode. figure 3-6. fifo data path functional diagram ?receive dmabufh dmabufl pfhr1 pfhr2 fifo (64 bytes) tag (64 bits) db[15:8] db[7:0] pfsr (receive) mux mux parallel port status tag tag tag bit tag bit status note: data does not move from the fifo to pfhr1 if the onechar status bit is true (see section 3.4.6 on page 27).
data book v2.0 october 1996 30 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.5.5 interrupts interrupts are enabled in the pcier and interrupt status can be read in the pcisr. these two regis- ters have the same format. 3.5.6 manual mode manual mode allows direct control of the ?e output control signals and the pd bus. it is not intended for data transfers, but rather for advanced diagnostics. enter manual mode by setting the manmd bit (pcr[7]) when the interface is in compatibility mode. the mmdir bit (pcr[1]) sets the direction of the pd bus: 0 = input; 1 = output. when the mmdir bit is set to ?? data for the pd bus comes from the mdr. the manoe bit controls the tristate buffer on the pd bus: 0 = ?ating; 1 = driving. when mmdir is ?? manoe is ignored, pd[7:0] are inputs, and the data can be read in the mdr. 3.5.7 control signals output signals are controlled by the ovr. the degree of control depends on the current mode. in manual mode, all ?e signals are under user control. in compatible and epp modes, only three signals are available, the others are set by the state machine. ivr, zdr, odr, and ssr monitor the four input sig- nals. these four registers have a common format. the ivr always shows the values of the four input pins. zdr and odr allow the user to force inter- rupts on speci? signal transitions. bits set in the zdr generate an interrupt, if the speci?d signal changes from ? to ?? similarly, bits set in the odr generate an interrupt if the speci?d signal changes from ? to ?? when both bits are set, interrupts are generated on either transition. the ssr shows the status of signal changes according to zdr and odr. ssr shows which signal changed. (it is nec- essary for the user to read the ivr to determine how the signal changed.) the signal change inter- rupt is enabled with the sigch bit (pcier[4]). figure 3-7. fifo data path functional diagram: transmit db[15:8] db[7:0] parallel port (transmit) dmabufh dmabufl pfhr1 pfhr2 fifo (64 bytes) tag (64 bits) pfsr tag tag tag bit status status
october 1996 31 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.5.8 parallel port interface to the fifo the dmadir bit indicates the current direction (0 = in; 1 = out) of transfers between the fifo and the dma logic. due to a recent negotiation, this can differ from the current parallel-port interface direc- tion. the cpu must change the direction after it receives an interrupt showing a direction change. the fifolock bit (pacr[4]) stops the dma pipeline. this can be useful in diagnostics. fifolock is also used in ecp and epp modes to stop data transfers in the forward direction. 3.5.9 ieee 1284-protocol negotiations all ieee 1284 protocol negotiations are initiated by the master side. the role of the cl-cd1283 is to accept or reject the attempted negotiation. the ner contains bits to individually enable speci? ieee 1284 modes. the various ieee 1284 modes require negotiations on the parallel interface before they can be entered. until a successful negotiation sequence is com- plete, the interface remains in compatibility mode. these negotiations occur in two stages; both stages occur automatically after the device is commanded to begin the negotiation procedure to a particular mode. the ?st stage determines if the slave is ieee 1284-compatible. once determined, the interface continues the process to determine if the mode requested is supported. the result of the requested negotiation appears in the nsr. for negotiations to occur, the slave must enable the e1284 bit (pcr[6]). data transfers require that the etxfr bit (pcr[5]) be set; negotiations can occur without data transfer enabled. negotiation status register after any ieee-1284 negotiation or termination, the current protocol status can be read in the nsr. negok and negfl (bits 7:6) indicate successful and failed attempts. invalid (bit 4) indicates that the mode terminated from an invalid state. termination from valid states are reported as successful with negok. a 4-bit code is displayed in the lower portion of the nsr to indicate the results of successful negotia- tion. the 4-bit code in nsr also indicates the mode that the interface was in when an invalid termination was detected, as well as a failed negotiation. inter- rupts indicating a successful negotiation into a reverse mode should prompt the cpu to load reverse data into the fifo. special command register the bits in the scr cause actions on the parallel port. setps and clrps (bits 3:2) control data move- ment into the cl-cd1283 from the remote master. in compatibility mode, this function posts error sta- tus to the remote. errors can only be presented to the master by the slave during the active busy period. setps causes the cl-cd1283 to stop trans- fers by asynchronously asserting the busy signal. to protect against the possibility of data loss, one more byte can be strobed into the cl-cd1283 after busy goes active due to the setting of setps. when the error status is delivered, clrps restores the par- allel interface to the normal running state. epirq sends an interrupt pulse in epp mode. the revrq bit indicates that data is available for reverse transfer in either compatibility or ecp mode. these operations are further described in the relevant pro- tocol sections. 3.5.10 data transfers in compatibility mode, incoming hstclk (strobe*) pulses activate perbsy (busy), and the data on pd[7:0] is held in latches. perbsy protects the data latches by signalling the master it is not ready for more transfers. after the hstclk pulse ends, a pulse is sent on perclk (ack*) to acknowledge the receipt of the data into the holding latches. after the data moves from the latches to the fifo, perbsy goes low to signal readiness for the next character. all other data transfer modes require ieee-1284 negotiations. 3.5.11 compatibility mode status the ieee 1284 speci?ation requires that the three compatibility mode status lines (select, fault*, and perror) must not be asserted unless perbsy (busy) is high. perbsy can only be activated in response to a received character, and must remain high until the status condition (for example, paper out) changes.
data book v2.0 october 1996 32 functional description cl-cd1283 ieee 1284-compatible parallel interface controller to send these status signals to the master device, set the setps bit (scr[2]) and the appropriate bit in the ovr for each of the status signals. the setps bit activates perbsy, which remains active until clrps (scr[3]) is set. no data is lost in this operation. 3.6 ieee 1284 parallel protocol support 3.6.1 compatibility mode compatibility mode provides backward compatibility with centronics and pc-compatible printer inter- faces. when the host parallel port is in compatibility mode (with no data transfer in progress), the host can initiate data transfers in compatibility mode or initiate negotiations to a new operating mode. only busy-while-strobe and ack-in-busy timing is supported in compatibility mode. busy-after- strobe, ack-after-busy, and ack-while-busy timings are not supported. figure 3-8. supported compatibility mode timing 3.6.2 reverse-nibble and reverse-byte modes these modes support reverse transfers only, from slave to master. reverse-nibble mode is enabled with ner[0]; reverse-byte mode is enabled with ner[1]. reverse-nibble mode sends 4 bits at a time over four of the peripheral status lines. with software drivers the advantage of this scheme is that any uni- directional pc parallel port can be used for bidirec- tional data transfers. reverse-byte mode requires bidirectional buffers on the pc hardware, but allows substantially faster transfers because it moves one byte at a time. there is no mechanism in compatibility mode for the slave to indicate that data is available for reverse transfers. the master must poll the slave by negoti- ating into a reverse mode and examining the ndatav signal. the revrq (scr[0]) instructs the cl-cd1283 to post the availability of data to the master through the ndatav signal. 3.6.3 id request id request is enabled with a combination of ner[6] and one of four other transfer mode bits. id requests can be made in conjunction with ecp, ecp/rle, reverse-byte, and reverse-nibble modes; there is no id request function de?ed for epp mode. the cl-cd1283 can accept an id request in any mode enabled to manage transfers. idreq is set when an id request is received in any enabled mode. 3.6.4 ecp mode ecp mode allows bidirectional transfers and sup- ports the rle-compression scheme. the ability to expand rle data is required of all ieee-1284, ecp- compliant devices, but the ability to compress data is optional. the cl-cd1283 handles both expan- sion and compression in the data path section. the parallel port simply passes the inverse of the com- mand signal to/from the fifo on the ninth tag bit in the fifo. ecp mode is enabled by ner[2]. rle mode enabling requires both ner bits 2 and 3. the handshake is identical for both ecp and rle modes. the control signals, hstbsy and perbsy (in the forward and reverse directions, respectively), indicate command and address options. if hstbsy/perbsy is low, the upper bit of the byte is examined: ? indicates to interpret the lower 7 bits as an address; ? indicates to use the lower 7 bits as an rle repeat count. this count shows the number of times to consecutively repeat that the next data character in the datastream. the master device is responsible for determining the direction of the transfer. the slave can request a direction change, but the master actually changes the direction. ecp mode always begins in the for- ward direction, from master to slave. the cpu sets the revrq bit (scr[0]) to request reverse transfers. once the master changes direction, revrq is auto- matically cleared and the dirch interrupt status appears in pcisr (if enabled in the pcier). nstrobe nack busy
october 1996 33 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller the master device switches the direction of the interface for forward transfers when the slave indi- cates no more data is available. 3.6.5 epp mode data transfers use the dma pipeline and the fifo. address transfers are handled out-of-band, not in the fifo stream. when the slave receives an address write command, it deposits the address into the ear and asserts an eppaw interrupt request. when the slave receives a read address command, the contents of the ear are returned. 3.7 protocol timing the ieee-1284 speci?ation timing parameter, t p , speci?s the minimum pulse width and the minimum setup time as 500 ns. the spr must be loaded with the number of system clock ticks equivalent to 500 ns, as shown in table 3-2. 3.8 general-purpose i/o port the cl-cd1283 provides an 8-bit general-purpose port (gp[7:0]) used to control or give status of exter- nal functions. each of the eight signals are individu- ally programmable for direction, so the port can be comprised of any number of inputs and outputs. each port signal is implemented with a standard, bidirectional hcmos pad and is fully ttl compati- ble. the port is controlled through two internal regis- ters ?gpdir and gpio. each bit in the gpdir sets the direction of the cor- responding bit in the gpio; ? sets the signal as output, and ? sets it as input. when writing to the gpio, only the bits programmed as outputs are affected by the contents of the data bus. when reading the gpio, bits programmed as inputs re?ct the true state of the condition of the external pin; bits programmed as outputs re?ct the state of the last value written to the register and the current state of the output pins. at reset, all bits in the gpio are cleared and the signals are programmed as inputs. note: interrupts are not generated on signal changes within the general-purpose i/o port; the cpu must periodically poll gpio to detect changes in external conditions. therefore, if it is neces- sary to detect changes, use the port with sig- nals that change with low-duty cycles. 3.9 parallel port interface the cl-cd1283 parallel port signals are imple- mented with level-2 characteristics, as de?ed in the ieee std 1284-1994 speci?ation with the exception of transient protection. as such, the port can be directly connected to the interface cable with the addition of a few external components. the components consist of passive pull-up resis- tors, series impedance matching resistors, and clipping diodes. additional noise ?tering may be required in an end system. figure 3-9 illustrates a typical interface with the components listed above. some system designs may require buffers between the cl-cd1283 and the cable. systems that require drive cables longer than the speci?d maximum of 10 m or those that need to protect the cl-cd1283 require inexpensive buffers between it and the cable. the device provides two signal out- puts, pdben and ebdir, for connecting and con- trolling buffers (such as, 74as245 or equivalent). these signals do not allow direct control of the buffer. however, the addition of an xnor gate pro- vides both an enable control signal and a signal to select the direction of the buffer. pdben and ebdir are outputs from the control state machine that indicate its current state (see figure 3-10 on page 35). table 3-2. system clock setup clk freq. (mhz) time/tic (ns) spr value t p width 16 62.5 8 500 20 50 10 500 25 40 13 520
data book v2.0 october 1996 34 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-9. cable connection +5 v 1.2 k w 20 w 20 w cl-cd1283 bidirectional signal line output signal line input signal line cable connector transient protection 1.2 k w caution: transient protection is not implemented inside the cl-cd1283 device, therefore transient voltages may cause damage. laboratory testing has shown that this type of protection is not necessary under normal conditions. however, damage may occur under harsh conditions or when subjected to unusual abuse. also note, the protection circuit shown here may cause a powered-up host to supply power to the +5 v (v cc ) of the peripheral if it is not powered up. if this is a concern, then another protection circuit must be designed.
october 1996 35 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller figure 3-10. external buffer control g dir ba to cable to cl-cd1283 pdben ebdir 74as245 impedance matching and protec- tion circuitry (see figure 3-9) as required for the 74as245. 3.10 hardware con?urations the simplicity of the cpu interface to the cl-cd1283 allows the device to be designed into systems that employ popular microprocessors such as the intel 80x86 family (8086, 80286, 80386, and so on) and the motorola a family (68000, 68010, 68020, and so on). an example of cl-cd1283 con?uration for a laser- printer application is shown in figure 3-11. this example provides a parallel interface, as well as general-purpose i/o for static control/status. figure 3-11. sample system block diagram cl-cd1283 rom address bus data bus control processor ieee 1284 parallel channel general-purpose i/o: internal status and control ram
data book v2.0 october 1996 36 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.10.1 interfacing to an intel a microprocessor-based system with very little additional logic, the cl-cd1283 can interface to any system based on a processor in the intel 80x86 family. figure 3-12 shows a generalized view of an i/o-mapped interface with an 80286- based system. to provide the proper strobes and controls, the ior* and iow* control strobes synthe- size the ds* and r/w* signals. dtack* is an input to wait-state-generation logic that holds the proces- sor (if necessary) until the cl-cd1283 completes the i/o request. figure 3-12. intel a 80x86 family interface 80x86 cl-cd1283 system cs* a[6:0] db[15:0] address data ior* iow* ds* r/w* a[23:7] a[6:0] ready dtack* svcreqp* svcackp* address decode logic wait-state generation logic irq inputs dmareq* dmaack* dma control
october 1996 37 data book v2.0 functional description cl-cd1283 ieee 1284-compatible parallel interface controller 3.10.2 interfacing to a motorola a microprocessor-based system interfacing to a motorola 68000 family device is rel- atively simple. bus timing and interface signal de? nitions closely match those of the 68000 microprocessor, which allows a direct connection. with later versions (68020, 68030), some additional logic is required to generate the dsack0* and dsack1* functions that replace the dtack* on earlier devices. figure 3-13 shows a generalized interface to a 68020 device. figure 3-13. motorola a 68020 interface 68020 cl-cd1283 system cs* a[6:0] db[15:0] address data ds* r/w* ds* r/w* ipl[2:0] a[31:9] a[8:2] dsack1* dtack* fc[2:0] as* dsack0* svcreqp* svcackp* address decode logic priority encoding transfer control dmareq* dmaack* dma control
data book v2.0 october 1996 38 programming cl-cd1283 ieee 1284-compatible parallel interface controller 4. programming 4.1 overview as shown in the register summary tables in chapter 2, the cl-cd1283 local cpu interface con- sists of a large array of registers. these registers control all aspects of device behavior. most registers are only modi?d once, during initialization, and rarely modi?d during normal operation. this chap- ter discusses these aspects, as well as the methods of interacting with the cl-cd1283 for parallel-chan- nel service requirements. 4.2 initialization to properly power-up a cl-cd1283 , several proce- dures must be completed. these include device ini- tialization, programming global functions, and setting port parameters. in most cases, initialization routines are only executed once ?during overall system boot-up. section 4.2.1 details these steps (see figure 4-1 on page 39 for a ?w-chart step out- line). 4.2.1 device reset the procedures that perform chip reset are normally executed after a power-up, system-wide reset. the hardware reset control signal, reset* causes the cl-cd1284 to perform its own internal initialization. if desired, the driver software can issue a full chip reset before chip initialization begins. to accomplish this, perform the following steps. 1. wait for rcr to contain ?x00? the contents of the rcr must be ? before the reset command is issued. this is required to ensure that the device is ready to accept the new com- mand. since this is probably the ?st command writ- ten to the cl-cd1283 after power-on initialization, the rcr is likely to be ?? but it is recommended to always check the rcr before writing a new com- mand. 2. set the aer ?x02? this is the only time during normal operation that the aer is set to any value other than ?x00? again, this is required to maintain binary compatibility with the cl-cd1284. 3. write hexadecimal 81 (x?1) to the rcr. this command causes the cl-cd1283 to perform a global reset. it causes the internal risc processor to begin execution from its power-up reset location. the results are the same as if the reset* input is activated. all internal interface registers are cleared, the fifo is ?shed, and all channel opera- tions are disabled. 4. wait for the ?mware revision code to be written into the gfrcr. internal ?mware uses this operation to ?g comple- tion of the reset procedure. after the reset is issued, the gfrcr is one of the ?st registers cleared and it is the last one set before normal runtime code execution begins. the initialization routine must wait for this register to become non-zero before it begins any other programming of cl-cd1284 registers. if the cpu is suf?iently fast, it could begin testing the gfrcr before the mpu clears it. the assumption could be made that the cl-cd1284 has completed internal initialization when, in fact, it has not even started. to avoid this error, the cpu should look for the gfrcr to change to ?? it should then look to the current revision code. alternatively, the cpu can clear the gfrcr just prior to issuing the global reset command and then poll for the correct revision code. this is useful in slow systems that cannot guarantee that the cpu can check the register after it is cleared or before it is loaded with the revision code. this procedure is also used as part of a diagnostic test suite. the device completes internal initializa- tion within 500 m sec. a timer (software or hardware) detects when the operation is not completed within that time and cues if the device is functional.
october 1996 39 data book v2.0 programming cl-cd1283 ieee 1284-compatible parallel interface controller figure 4-1. flow diagram of the cl-cd1283 master initialization sequence gfrcr = 0 ? issue reset command n y gfrcr = 25* ? n y continue init process * revision code for revision e device = 25 future revisions, if rcr = 0 ? n y this by one; for example, revision f would be 26, etc. necessary, will increment clear gfrcr
data book v2.0 october 1996 40 programming cl-cd1283 ieee 1284-compatible parallel interface controller the following section of programming code shows a typical initialization sequence preparing the par- allel channel for compatibility mode data reception and enabling negotiation into all modes, except epp. this procedure can also be used as part of a diagnostic test suite. the device will complete internal initialization within 500 m sec. therefore, a timer (software or hardware) can be used to detect that the operation does not complete within this time and that the device may not be functional. /* initialization of the parallel channel consists of setting the spr, selecting modes that will be supported during negotiation, stale data timeout value, initalizing the fifo, the source for interrupts that will be accepted and other operational functions. */ par_init() { /* first, issue chip reset command */ outportb(gfrcr, 0x00); /* clear the gfrcr */ outportb(aer, 0x02); /* aer must equal 02h or o3h to access rcr*/ while (inportb(rcr) != 0x00) ; /* wait for rcr to clear */ outportb(rcr, 0x81); while (inportb(gfrcr) != 0x00); /* wait for gfrcr to be cleaared */ while (inportb(gfrcr) != 0x25); /* wait for gfrcr to be set */ /* start by initializing the parallel channel */ outportb(aer, 0x00); /* set the access enable register */ outportb(spr, 0x0d); /* assume 25mhz clock, set short pulse value */ outportb(ner, 0x4f); /* support all modes except epp */ outportb(ovr, 0x18); /* start in compatibility mode, set status signals: */ /* perror = 0 */ /* selct = 1 */ /* nfault = 1 */ outportb(pcier, 0x37); /* enable all interrupts except epp address write */ outportb(pcr, 0x60); /* enable 1284 negotiations and transfers */ /* next, set up the pipeline control registers */ outportb(livr, 0x00); /* initialize the interrupt vector to 0 */ outportb(pfcr, 0xd8); /* enable pipeline dma, set the direction to input, */ /* enable interrupts (but not error ints) and reset*/ /* the fifo. at reset, it is assumed that the starting */ /* direction will be input. */ outportb(pfcr, 0x58); /* remove reset */ outportb(pftr, 0x20); /* set the dma threshold for receive (burst = 32) */ outportb(sdtpr, 0x64); /* set the stale data timeout period to 10ms */ outportb(pacr, 0x02); /* set asynchronous dma mode */ }
october 1996 41 data book v2.0 programming cl-cd1283 ieee 1284-compatible parallel interface controller 4.2.2 service acknowledge handling service request and acknowledge processing, as well as dma request and acknowledge process- ing, is performed by the internal mpu. it is impor- tant to take the behavior of the mpu into account if interrupts are used. there are two different varia- tions where service requests can be serviced. one variation uses the svcackp*, the other does not. if the svcackp* signal is activated through an input instruction then the device will return the value of the livr on the data bus. this can be used as a vector to the service routine or used in a switch instruction to jump to the correct routine. when the svcack* is activated, the svcreqp* is deactivated. if the svcackp* signal is not acti- vated, then the service request must be removed by clearing ppireq (pir[7]), and the source of the interrupt must be determined by reading the livr, pivr, or pir. regardless of the variation per- formed, inten (pfcr[4]) must be toggled at the end of the service routine to inform the device that the service routine has terminated. service_par( ) { char livr_val; if (inportb(svrr & 0x08)) { /* check for active service request */ livr_val = inportb(livr) & 0x07; switch (livr_val) { case 4: /* just the parallel channel state-machine request is active */ service_par_chan(); break; case 5: /* just the data path pipeline request is active */ service_pipeline(); break; case 6: /* both requests are active */ service_par_chan(); service_pipeline(); break; default: break; } outportb(pfcr, inportb(pfcr & 0xef);/* terminate service ack. sequence by */ outportb(pfcr, inportb(pfcr | 0x10);/* toggling inten bit in pfcr */ return(0); } }
data book v2.0 october 1996 42 programming cl-cd1283 ieee 1284-compatible parallel interface controller figure 4-2. polling flow chart hardware reset test svrr service negotiation change set software reset initialize device test pir test pfsr service dma request dmareq poll device again service change service change direction return id to host reset printer test pcisr test nsr test ssr test pfsr test hrsr = 00h srp set = 00h pipeline set pport set dirch idreq ninit negch set fifo dataerr signal interrupt service error interrupt service holding appropriate register or ff full empty or hr data hr tag poll device again sigch note: it may not be necessary to poll the pfsr if dma requests are enabled. with dma requests enabled, the dmareq bit (svrr[7]) can be polled to determine when a fifo threshold is exceeded. if dma requests are disabled, the pfsr register must be polled to determine when to move data to and from the fifo. if dma requests are enabled, data must be read through the dmabuf register; this requires a 16-bit data bus.
october 1996 43 data book v2.0 programming cl-cd1283 ieee 1284-compatible parallel interface controller 4.3 ascii code tables table 4-1. hexadecimal ?character 00 nul 01 soh 02 stx 03 etx 04 eot 05 enq 06 ack 07 bel 08 bs 09 ht 0a nl 0b vt 0c np 0d cr 0e so 0f si 10 dle 11 dc1 12 dc2 13 dc3 14 dc4 15 nak 16 syn 17 etb 18 can 19 em 1a sub 1b esc 1c fs 1d gs 1e rs 1f us 20sp21 ! 22 23#24$25%26&27 28(29)2a*2b+2c,2d-2e.2f/ 300311322333344355366377 3883993a:3b;3c<3d=3e>3f? 40@41a42b43c44d45e46f47g 48h49 i 4aj4bk4cl4dm4en4fo 50p51q52r53s54t55u56v57w 58 x 59 y 5a z 5b [ 5c \ 5d ] 5e ^ 5f _ 60~61a62b63c64d65e66 f 67g 68 h 69 i 6a j 6b k 6c l 6d m 6e n 6f o 70p71q72r73s74 t 75u76v77w 78 x 79 y 7a z 7b { 7c | 7d } 7e _ 7f del table 4-2. decimal ?character 0 nul 1 soh 2 stx 3 etx 4 eot 5 enq 6 ack 7 bel 8 bs 9 ht 10 nl 11 vt 12 13 13 cr 14 so 15 si 16 dle 17 dc1 18 dc2 19 dc3 20 dc4 21 nak 22 syn 23 etb 24 can 25 em 26 sub 27 esc 28 fs 29 gs 30 rs 31 us 32sp33 ! 34 35#36$37%38&39 40(41)42*43+44,45-46.47/ 480491502513524535546557 56857958:59;60<61=62>63? 64@65a66b67c68d69e70f71g 72h73 i 74 j 75k76l77m78n79o 80p81q82r83s84t85u86v87w 88x89y90z91[92\93]94^95_ 96 ~ 97 a 98 b 99 c 100 d 101 e 102 f 103 g 104 h 105 i 106 j 107 k 108 l 109 m 110 n 111 o 112 p 113 q 114 r 115 s 116 t 117 u 118 v 119 w 120 x 121 y 122 z 123 { 124 | 125 } 126 _ 127 del
data book v2.0 october 1996 44 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5. detailed register descriptions this section presents a detailed description of each register. registers have two formats: full eight bits, where the entire content de?es a single function; or the register is a collection of bits, grouped singly or in multiples, de?ing a function. in the second case, the descriptions divide the register into its component parts and describe the bits individually. the registers are presented in the same order as outlined in chapter 2. bits de?ed as ? should not be modi?d and, if values other than ? are read, program exe- cution should not be affected or software compatibility with future revisions will be uncertain. 5.1 global registers 5.1.1 access enable register the aer provides binary compatibility with the cl-cd1284. users must program this register with the least-signi?ant bits set to ? to access the parallel channel; however, to perform a device reset through the rcr, aer must = 02h. the contents of the upper 5 bits should be ignored when read. 5.1.2 global firmware revision code register the gfrcr serves two purposes in the cl-cd1283. first, it displays the revision number of the ?mware in the device. when a revision to the cl-cd1283 is required, the revision number of the ?mware is incre- ments by one. the revision code is 24 (hex) for the revision d device, and 25 (hex) for the revision e device. secondly, this register can be used by the system programmer as an indication of when the internal pro- cessor has completed reset procedures, after either a power-on reset (through the reset* input) or a software global reset (through the reset command in the ccr). immediately after the reset operation begins, the internal cpu clears the register. when complete, and the cl-cd1283 is ready to accept host accesses, the register is loaded with the revision code. register name: aer register description: access enable access: r/w 8-bit hex address: 68 default value: xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxx0 0 0 register name: gfrcr register description: global firmware revision code access: r/w 8-bit hex address: 4f default value: 25 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 firmware revision code
october 1996 45 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.1.3 general-purpose i/o direction register 5.1.4 general-purpose i/o register the gpdir and gpio registers enable access and control of the general-purpose i/o port. the general- purpose i/o port provides a byte-wide general purpose set of signals that are individually direction pro- grammable. the gpio register accesses the data port on pins 53?0 (g[7:0]) with data0 accessing gp[0], and so on. the corresponding bit in the gpdir controls the direction of the associated signal; a logic ? programs the signal as output, and a logic ? programs it as input. when writing to the gpio register, ?s and ?s are re?cted in their true states on the pins that are pro- grammed as outputs. when reading from the gpio register, bits programmed as inputs re?ct the true state of the signal condition on those bits; bits programmed as output will re?ct the previously set state. register name: gpdir register description: general-purpose i/o direction access: r/w 8-bit hex address: 71 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir7 dir6 dir5 dir4 dir3 dir2 dir1 dir0 register name: gpio register description: general-purpose i/o access: r/w 8-bit hex address: 70 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data7 data6 data5 data4 data3 data2 data1 data0
data book v2.0 october 1996 46 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.1.5 parallel interrupt register the pir indicates the source of service requests being presented by the parallel channel, either from the parallel port or from the pipeline. 5.1.6 prescaler period register the ppr sets the divisor used to generate the time period for cl-cd1283 timer operations. it can be set to any value between 0 and 255 (x?f). the ppr is clocked by the system clock prescaled (divided) by 512. for best device operation, the value loaded into the ppr should not be less than x?0. register name: pir register description: parallel interrupt access: r/w 8-bit hex address: 61 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppireq pport pipeline 00000 bit description 7 ppireq: internal logic sets this bit to generate the external service request output. it is a direct re?ction of the inverse state of the svcreqp* pin; it is the active-high output of the latch that drives the svcreqp* pin. this bit can be scanned by the host to detect an active service request. this bit is cleared by the inter- nal logic at the beginning of the hardware service-acknowledge cycle or by toggling inten (pfcr[4]). clearing pir automatically deactivates the svcreqp* output and clears the srp bit (svrr[3]). 6:5 pport and pipeline: these two bits indicate which of the two functional blocks of the parallel port are requesting service. when pport is set, it indicates that the parallel channel control state machine is the cause of the request; when pipeline is set, it indicates that the data pipeline is requesting service. if both bits are set, it indicates that both blocks are requesting service simultaneously. 4:0 reserved: the remainder of the bits in the pir always return ? when read by the host and should not be modi?d. register name: ppr register description: prescale period access: r/w 8-bit hex address: 7e default value: ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 binary value
october 1996 47 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.1.7 service request register the svrr re?cts the inverse of the state of the service request pins (dmareq* and svcreqp*). its primary use is in polled systems, and it allows system software to determine what, if any, service requests are pending. register name: svrr register description: service request access: read only 8-bit hex address: 67 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dmareq x x x srp x x x bit description 7 dma request status: when this bit is set to ?? it indicates that a request is pending. 6:4 these bits are not used and are don? cares. 3 service request parallel: when this bit is set to ?? it indicates that a request is pending. 2:0 these bits are not used and are don? cares.
data book v2.0 october 1996 48 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.2 virtual registers the cl-cd1283 has two operational contexts: a normal context that allows host access to most registers and any channel, and a service-acknowledge context, allowing host access to some registers speci? to the channel requesting service. this special set of registers is called ?irtual because they are only avail- able to host access and are valid during this service-acknowledge context; at all other times, their con- tents will be unde?ed and must not be written to by host software. the use of virtual registers and context switching allows the cl-cd1283 to maintain all channel-speci? information. the host need not make any changes to chip registers to access the registers pertinent to the parallel channel. the service-acknowledge context is entered in one of two ways: either through activation of the svcackp* input pin (hardware activated), or through host software when the contents of any one of pir is copied into the aer by host software during a poll-mode acknowledge cycle (software-activated). see chapter 3 for a discussion of the differences between these two modes. 5.2.1 end-of-service request register the eosrr is a ?ummy location and is used to signal the end of a hardware-activated service-acknowl- edge procedure, invoked by the activation of svcackp*. the data pattern written is a ?on? care value. writing this location causes the cl-cd1283 to perform its internal switch out of the service-acknowledge context. this register is used only during a hardware-activated service acknowledge and must not be writ- ten during poll-mode operation. register name: eosrr register description: end-of-service request access: write only 8-bit hex address: 60 default value: xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx
october 1996 49 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.2.2 parallel interrupt vector register the value in this register is placed on the data bus, db[7:0], when svcackp* is activated in response to an active svcreqp*. see section 5.3.5 on page 54 for more details on the livr. register name: pivr register description: parallel interrupt vector access: read only 8-bit hex address: 40 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user-de?ed ?upper 5 bits of livr it2 it1 it0 table 5-1. pivr[2:0] encoding it2 it1 it0 description 0 0 0 no active interrupt. 001 invalid. 0 1 1 1 0 0 the parallel channel state machine requests service. 1 0 1 the parallel channel data pipeline requests service. 1 1 0 both the parallel port state machine and the parallel port data pipeline request service. 1 1 1 invalid.
data book v2.0 october 1996 50 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3 parallel pipeline registers 5.3.1 data error register the bits in this read-only register indicate read/write errors involving the dma buffer register and the data pipeline registers. the dataerr bit in pfsr is the logical or of these eight error status bits. a read of this register has no effect on the error status. a write to this register clears all bits; they are not individually writable by the user. host software should clear this register (write x?0) after completing an error service-acknowledge procedure. this bit is provided primarily as an aid to driver software develop- ment. under normal circumstances, data errors should never occur. this register is cleared during device reset. register name: der register description: data error access: read only 8-bit hex address: 33 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dmawrerr dmarderr bufwrerr bufrderr hr1wrerr hr1rderr hr2wrerr hr2rderr bit description 7 dma write error: this bit is set if the dma control logic has written to the dma buffer when it already contains data. it indicates that an invalid dma transfer cycle occurred (a dmaack* without a corresponding dmareq*). 6 dma read error: as with bit 7, this bit indicates that dma logic has performed a read from the dma buffer when there was no data in it. it indicates that an invalid dma transfer cycle occurred. 5 buffer write error: this bit indicates that a system write to the dma buffer occurred while it still contained data. 4 buffer read error: this bit indicates that a system read from the dma buffer occurred while it was empty. 3 holding register 1 write error: this bit indicates that a system write to pfhr1 (parallel fifo holding register 1) occurred while it still contained data. 2 holding register 1 read error: this bit indicates that a system read from pfhr1 occurred while it was empty. 1 holding register 2 write error: this bit indicates that a system write to pfhr2 (parallel fifo holding register 2) occurred while it still contained data. 0 holding register 2 read error: this bit indicates that a system read from pfhr2 occurred while it was empty.
october 1996 51 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.2 dma buffer data register this 16-bit data register is used to buffer dma data transfers to and from the cl-cd1283. under normal operating conditions, this register is only accessed during a dma data transfer cycle. if dmabufwe (pfcr0) is set to ? and dmadir (pfcr[5]) is set to ?? 16-bit data can be transferred from the host to the fifo by directly writing to the dmabuf. the data automatically moves forward into the fifo through the data pipeline holding registers. the user must ensure that the fifo has suf?ient free space to accept the data before writing into the dmabuf. the byteswap pin determines the order of byte transfer from this register into the data pipeline. if byteswap is set to ?? data transferred on db[15:8] is the ?st byte transferred into the data pipeline and db[7:0] is transferred second. if byteswap is set to ? this sequence is reversed. the same applies during data read during dma transfers: if byteswap is set to ?? data from the data pipeline moves to the upper byte of dmabuf, the next byte moves into the lower byte. again, if byteswap is set to ?? this sequence is reversed. these resisters can be read through dma acknowledge or pio cycles. however, the dmabuf registers can only be read when the dmareq* signal is active. if dmareq* is inactive, the dmabuf registers will be empty. dmafull (hrsr[3]) indicates if the dmabuf register is empty when dmareq* is inactive. register name: dmabuf register description: dma buffer data high access: r/w 8-bit hex address: 30 default value: 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dma buffer data high byte register name: dmabuf register description: dma buffer data low access: r/w 8-bit hex address: 30 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dma buffer data low byte
data book v2.0 october 1996 52 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.3 holding register status register the hrsr is read-only and indicates current data pipeline status this register is not directly set to any particular value at device reset, but re?cts the current state of bits in other registers. register name: hrsr register description: holding status access: read only 8-bit hex address: 34 default value: 04 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hr1full hr1tag hr2full hr2tag dmafull dmampty dmaact ctnot0 bit description 7:6 hr1full and hr1tag: these two bits indicate status of pfhr1. bit 7 indicates that the register contains data and bit 6 indicates that the data is tagged. both bits can be set simultaneously. 5:4 hr2full and hr2tag: these two bits indicate status of pfhr2. bit 5 indicates that the register contains data and bit 4 indicates that the data is tagged. both bits can be set simultaneously. 3:2 dmafull and dmampty: these two bits indicate status of the dma transfer buffer (dma buffer). bit 3 indicates that the register contains data and bit 2 indicates that it is empty. 1 dmaact: this bit when set, indicates that the dma handshake is active and that dma service is requested, but not yet complete (dmareq* active, waiting for dmaack*). 0 ctnot0: this bit indicates that the rle counter is not zero, thus run-length encoding/decoding is in progress.
october 1996 53 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.4 host timeout value register hvtr holds the 8-bit value used to set the host timeout period. the htvr is an unsigned, binary value. the reset state of this register is ?xff? a function missing in the revision ? and earlier devices is an on-chip timer to indicate that the remote host has not responded in a speci?d time period. the host timeout is de?ed in the ieee std 1284 speci?ation as a period of one second. the revision ? device adds a user-programmable timer that provides a timeout if the remote host does not respond to speci? parallel port transactions. the timer is started by the parallel port state machine each time it starts a sequence requiring a host response. activation of the timer is automatic and an inter- rupt is generated to the local host cpu if the timer expires before the remote host responds. note: users familiar with the ieee speci?ation note that the events that start the timer cause the peripheral device to move to a state where it waits for a remote host-generated event. for example, during the negoti- ation sequence after event 2, the peripheral waits for event 3, a host-generated event. if the host does not respond and moves the negotiation sequence to event 4 within one second, the peripheral enters the ?ost timeout condition. the timer is a 14-bit counter clocked by the system clock (clk) prescaled (divided) by 2048. program the 8-bit host timeout value register (htvr, address offset 0x?4), which is then compared with the most- signi?ant 8 bits of the 14-bit counter. each time the parallel port executes an event requiring a host response, the 14-bit counter is started (from 0x?0). it counts up until either the expected event occurs or the count matches the value in htvr. if a match occurs, a timeout condition exists. the htvr need only be loaded once, typically during device initialization. the value placed in htvr yields an approximate one second count time, based on the value of the input clk. for example, if the system clock driving the device is 25 mhz, the htvr should be loaded with 0xc0. equation 5-1 provides an example. equation 5-1 the computed value is rounded up to the next largest whole hex value, in this case ?x3000? load htvr with the most-signi?ant 8 bits of this value, left-shifted two places since htvr is a 14-bit counter. this results in a value of ?xc0? for 20 mhz, the value is computed to be ?x9c and for 16 mhz, the value is ?x7c? values for other clocks can be easily computed in the same manner. at reset, the htvr defaults to a value of ?xff? this prevents the extremely short timeouts that occur if the register is cleared at device reset and not initialized. a timeout causes a negotiation status change interrupt. this status is displayed as 0x22 in the negotiation status register (host timeout (bit 5), and the code for return to compatibility mode (0010) in the result code ?ld). when compatibility mode is reentered, the port control state machine waits in a locked state until signals on the parallel port return to normal compatibility mode conditions. for debug purposes, disable the host timeout timer by setting pcr bits 2 and 3 (host timer test [1:0]). in this case, no timeouts occur and the link can hang inde?itely while waiting for a host-generated event. register name: htvr register description: host timeout value access: read/write 8-bit hex address: 24 default value: ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host timeout period 25 mhz 2048 ------------------ 12207 10 2 faf 16 ==
data book v2.0 october 1996 54 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.5 local interrupt vector register this read/write register can be initialized to any desired value and, when read in the normal context (that is, not a service acknowledge context), the same value is returned. the upper 5 bits are copied into the appropriate vector register, pivr when the svcackp* signal is activated and svcreqp* is active. dur- ing this hardware-activated service acknowledge read cycle, the pivr is driven onto the data bus, db[7:0]. bits 7:3 come from livr and bits 2:0 are supplied by the cl-cd1283 (see section 5.2.2 on page 49 for details). this value can be used as a vector into the appropriate service routine (typical in motorola-type systems) or as a device identi?r for systems with multiple, daisy-chained cl-cd1283s. bits 2:0 are ignored. initialization of this register is only necessary if vectored interrupts are used. register name: livr register description: local interrupt vector access: r/w 8-bit hex address: 18 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user-de?ed bits x x x bit description 7:3 user-de?ed interrupt vector: host software can use these ?e bits for any purpose appropriate to the application. in some cases, these bits might de?e the rest of a complete interrupt response vector (motorola- type systems). in the case of daisy-chain systems made up of multiple cl-cd1283s, these bits are used to de?e the device number in the chain. 2:0 these bits are ?on? cares?
october 1996 55 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.6 parallel auxiliary control register the pacr provides some special functions for the parallel data path and interrupt-generation circuitry. the upper 2 bits are used to change the basic timing of the timers associated with the data pipeline. bit 5 can disable the stale data time. register name: pacr register description: parallel auxiliary control access: r/w 8-bit hex address: 3f default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 shrtten shrtstal staleoff fifolock clearto 0 asyncdma 0 bit description 7 shrtten: this function shortens the prescaler count cycle that generates the internal 10- m s clock (based on a 25-mhz system clock) for the stale data counter. this bit is cleared by reset*. if set, 10- m s ?icks of the counter will be generated every two clks; the normal period is one ?ick every 250 clks. 6 shrtstal: this function shortens the period of the stale data timer. the stale data timer includes a divide-by-ten prescaler; setting this bit bypasses the prescaler function, causing the stale data timer to count on each 10- m s clock ?ick? if both shrtten and shrtstal are set, the stale data timer counts on every other clk. 5 staleoff: when this bit is set, it masks off the stale status bit. the inverse of this bit is and?d with the stale state condition of the parallel channel to produce the stale status and has the effect of disabling onechar and stale as interrupt sources. staleoff is provided primarily for test and development purposes, when slow movement of data into the parallel port might cause stale and onechar to always appear true. 4 fifolock: this bit causes the fifo to stop accepting data from the parallel channel state machine. this action makes the fifo appear full to the parallel port, thus causing it to enter the ?usy state. this function is primarily intended for use in system testing to cause a timeout on the 1284 bus. setting this bit in ecp forward mode may cause a stall condition event 35 because event 36 will not occur until fifolock is cleared. the ecp mode host transfer recovery handshake sequence (from event 35 stall) is supported and the byte transit discarded as required by the speci?ation. this bit does not provide an effective means to ?w control the host. 3 clearto: the clear timeout bit is a reset bit for the timeout status latch logic. when toggled by software, the time- out status in the pfsr is cleared; it may be left set to disable the timeout status function. note that if this bit is left set, the onechar interrupt condition will never become true since there will be no fifo timeout activity. 2 reserved: this read-only bit is always ?? 1 asyncdma: this bit causes the device to synchronize the dmaack* signal to the internal clock (rising clock edge). this capability provides an asynchronous dma interface for systems that cannot meet the setup times required by the synchronous dma logic. refer to the section 6.4.1 on page 73 for speci? timing relationships between clk and dmaack* when asyncdma is enabled. 0 reserved: this read-only bit is always ??
data book v2.0 october 1996 56 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.7 parallel channel reset register this register can be used to issue a hardware reset to the parallel channel. 5.3.8 parallel fifo control register this register controls overall function of the parallel fifo. these include resetting (?shing) the fifo, enabling dma transfers, enabling host interrupts, run-length encoding, and so on. the host sets these bits according to the mode of operation desired. after hard reset (either through the reset* input pin or by setting bit 0 in the pcrr), this register is cleared to all zeroes. register name: pcrr register description: parallel channel reset access: r/w 8-bit hex address: 6c default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000000 pchreset bit description 7:1 these bits are not used and must always be ?? 0 pchreset: when this bit is set, it asserts the equivalent of a hardware power-on reset to the parallel channel, channel 0. if set by the host, pchreset must be cleared to resume normal parallel channel operation. this hard- ware reset affects only the parallel channel and has no effect on other functions of the device. register name: pfcr register description: parallel fifo control access: r/w 8-bit hex address: 31 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fifores dmaen dmadir inten rleen settag erren dmabufwe bit description 7 fifo reset: this bit must be set together with the correct value of dmadir to properly initialize the data pipeline and fifo registers for data transfer or when a new data transfer direction is desired. data remaining in the fifo is discarded. 6 dma enable: this bit must be set for dma requests to move data to/from the fifo. when dmaen is set to ?? the pfqr quantity value is compared with the pftr user-programmed threshold value. in receive mode, if the threshold is equalled or exceeded, dmareq* is asserted to cause dma data transfers of whole (2-byte) words from the fifo through the data pipeline. in transmit mode, if the amount of data in the fifo is equal or less than the threshold, dmareq* is asserted to cause dma data transfers of whole (2-byte) words to the fifo through the data pipeline. 5 dma direction: this bit sets the direction of transfer between the parallel fifo and system memory. if dmadir is set to ?? the direction is transmit (system memory to the parallel fifo); if it is ? the direction is receive. the desired dmadir value must be set together with fifores when initializing the fifo logic for data transfer. once a dmadir value is set and the fifores is complete, that dmadir selection must be maintained during any other changes to the control bits of the pfcr.
october 1996 57 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.9 parallel fifo empty pointer register this register contains the internal empty location pointer of the fifo. it identi?s the location in the fifo from which the next byte of data will transfer from the fifo. the pfep register is cleared by a device or fifo reset. 5.3.10 parallel fifo fill pointer register this register holds the internal ?l location pointer of the fifo. it identi?s the location in the fifo to receive the next data byte from the pipeline. the pffp register is cleared by a device or fifo reset. 4 interrupt enable: this is the master interrupt enable for the parallel channel. this bit must be set for any interrupts to be generated by the data pipeline, parallel port, or error status. in poll-mode operation, host software may toggle this bit to signal the completion of the service-acknowledge cycle and clear the current status in the pir, svrr, and livr. toggling this bit updates the state of svcreqp* and the pir according to the current state of pcisr, derr and pfsr. for this reason, pcisr, derr, and pfsr should be read and cleared at the beginning of the service routine. these registers should be checked again at the end of the service routine to ensure that no requests were skipped because an edge-sensitive interrupt controller may not detect a request that is already active when the program returns from the service routine. 3 rle enable: this bit enables run-length encoding/decoding for direction de?ed by dmadir. the rleen bit affects the ?w of data through the data pipeline in the transmit direction. data ?w into the fifo is managed in so that the pfhr1 and pfhr2 are kept full to permit evaluation of data sequences for possible compression. the effect is that following any data transfer while rleen is set, the ?al 2 bytes written to the dmabuf register are kept in pfhr1 and pfhr2. to allow these bytes to be moved into the fifo or to make room in pfhr1 for a tagged data transfer, rleen must be ? and both dmaen and dmabufwe must be ?? 2 set tag: this bit speci?s that the next character written to the parallel channel through the pfhr1 is to be tagged as an ecp or epp special character. this bit is cleared by the write to pfhr1, thus this bit must be set each time a tagged character is to be written. 1 error interrupt enable: this bit enables a non-zero dataerr status to cause an interrupt (if inten is also set). 0 dma buffer write enable: this bit must be set to enable host writes to the dmabuf register. it also enables the fifo data pipeline to empty dmabuf when it has been written to by the host system. in this case, the system will write to the dma buffer and not use dma transfers, providing a low-performance alternative to dma transfers. register name: pfep register description: parallel fifo empty pointer access: r/w 8-bit hex address: 39 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 6-bit binary fifo pointer value register name: pffp register description: parallel fifo fill pointer access: r/w 8-bit hex address: 38 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 6-bit binary fifo pointer value bit description (cont.)
data book v2.0 october 1996 58 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.11 parallel fifo holding registers these two 1-byte registers provide a data pipeline between the fifo and dma buffer. data always ?ws ?st into pfhr1, then to pfhr2 and ?ally, either to the fifo or the dmabuf register. the ?w is to the fifo if dmadir is a ?? and from the fifo if dmadir is ?? the pipeline and the holding registers support ?agged data for complete support of the ecp parallel port mode. tagged data is either an address code or a run-length code. in the receive direction (if rleen is set in the pfcr), run-length codes are captured in the rlcr for decompression of received data. ecp address codes are recognized and pass into the pfhr1?fhr2 pipeline. the presence of an ecp address will interrupt dma ?w and cause an interrupt to the host so it can remove the tagged data from the pipeline by reading either pfhr2 or pfhr1. in the transmit direction, the host may introduce ecp address (tagged) data or run-length codes for pre- compressed data by setting the settag bit in pfcr and writing the byte to be tagged to pfhr1. the settag bit must be set prior to writing to pfhr1 for each tagged data transfer. to perform a tagged data transfer, the automatic dma function must be disabled prior to the transfer (set dmaen to ??. this can be done at the same time that settag is set to ?? these registers are cleared by device or fifo reset and marked as empty in hrsr. any tagged status is also cleared. 5.3.12 parallel fifo quantity register this register maintains the quantity (or count) of either data bytes or space available in the parallel fifo. in the receive direction (dmadir is set to ??, pfqr counts data characters in the fifo. in the transmit direction (dmadir is set to ??, pfqr counts space available in the fifo for additional characters to trans- mit. fifores together with the value of dmadir initialize pfqr to either x?0 (receive) or x?0 (transmit). in either case, the pfqr indicates only the quantity of data or space available in the fifo, and does not include the data pipeline registers. register name: pfhr1 register description: parallel fifo holding register 1 access: r/w 8-bit hex address: 35 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit character data register name: pfhr2 register description: parallel fifo holding register 2 access: r/w 8-bit hex address: 36 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit character data register name: pfqr register description: parallel fifo quantity access: r/w 8-bit hex address: 3a default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data or space available in fifo ?max x?0
october 1996 59 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.13 parallel fifo status register the pfsr is read-only and provides current fifo and data pipeline status. host software should examine these bits in response to pipeline interrupts or for polling operations. this register is not directly cleared by reset, but the individual bits will re?ct the status of other registers. this register is cleared by device or fifo reset. register name: pfsr register description: parallel fifo status access: read only 8-bit hex address: 32 default value: 40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fffull ffempty timeout hrtag hrdata stale onechar dataerr bit description 7 parallel fifo full: if this bit is set, it indicates the parallel fifo is full. 6 parallel fifo empty: if this bit is set, the parallel fifo is empty. 5 timeout: this bit is set when stale goes from false to true. in the receive direction, timeout is delayed until the fifo is empty and all dma cycles are complete. timeout is a pipeline-interrupt condition and must be cleared manually by the cpu by toggling clearto in the pacr or by a fifo reset in the pfcr. 4 holding register tag: this bit indicates that a tagged character is in either the pfhr1, pfhr2, or both. this bit being set will cause a host interrupt to be generated (if enabled). the host should examine the hrsr to determine the exact cause(s) of this bit being set. 3 holding register data: if this bit is set, it indicates that either the pfhr1, pfhr2, or both contain data. 2 stale: this bit is set when the stale data timer expires (see description of sdtpr). if a single byte remains in the data pipeline when this bit is set, a host interrupt is generated, the onechar bit is set, and new data entering the fifo will not move into pfhr1 until pfhr2 is emptied. if two or more bytes remain in the pipeline when this bit is set, a host interrupt is not generated, however, a dma request will be generated if enabled. 1 one character: in the receive direction, when this bit is set it indicates that the fifo is empty and stale, and one character remains in the pfhr2. this condition occurs if an odd number of bytes is transferred through the parallel interface. since dma cycles only moves an even numbers of bytes (words), an odd transfer leaves one byte remaining. host software must remove this character outside of dma transfer cycles. 0 data error: when this bit is set, it indicates that one or more of the bits in the der (data error register) is set.
data book v2.0 october 1996 60 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.14 parallel fifo threshold register this register sets the fifo threshold for initiating dma requests for data transfer. the value is expressed in bytes. whenever dmaen is true, regular comparisons are made between the pfqr (parallel fifo quantity register) and the pftr. if the value in the pfqr is greater than or equal to the threshold, the dma request logic becomes active and remains active until the fifo is essentially ?led or emptied. an odd character or space in the fifo may remain. in the receive direction, the holding register pipeline (consisting of pfhr1 and pfhr2) and dmabuf (if dma is enabled) are kept ?led so that tagged data (for example, ecp-mode addresses) can be detected and passed to the host via an interrupt. if the fifo and data pipeline are initialized for receive and, for example, 40 hex bytes are placed into the fifo from the parallel port, the ?st two of those bytes is auto- matically placed in the pipeline registers. if the pftr were programmed to x?0 bytes, x?4 bytes must arrive to trigger a dma transfer. pftr is cleared by a device reset; it is not cleared by fifores. 5.3.15 run-length count register this register works with pfhr1 and pfhr2 to perform run-length encoding/decoding when the rleen bit (pfcr[3]) is set (the parallel port must be in ecp mode; in other modes, run-length encoding will not occur). in the transmit direction, strings of three or more identical characters are recognized and compressed. the running count of identical characters is kept in the rlcr. once the sequence is broken by a different character or the end of the transmit burst transfer, the count and a single copy of the duplicated character are put in the fifo. in the receive direction, run-length codes can be received from the remote device. these codes are rec- ognized ?n the ? as data ?ws from the fifo through the holding register pipeline. a run-length code is diverted to the rlcr. the subsequent character from the fifo is duplicated (held in pfhr1) while the rlcr is decremented. once the rlcr reaches zero, normal pipeline data movement is resumed. if run- length codes are being received by the parallel port but rleen is not set, the codes will enter pfhr1 and pfhr2 as tagged data and cause interrupts to the host. the host must directly read the tagged holding register to remove the character from the pipeline and clear the tag. register name: pftr register description: parallel fifo threshold access: r/w 8-bit hex address: 3b default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 dma transfer threshold register name: rlcr register description: run-length count access: r/w 8-bit hex address: 37 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 7-bit unsigned binary count
october 1996 61 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.3.16 stale data timer count register this register determines the period used to signal stale data in the fifo. the timer is used only in the receive direction. each time a new character is placed in the fifo from the parallel port, the sdtcr is reloaded from the sdtpr and down-counting begins at the tick rate. if the counter reaches zero, the stale bit (pfsr[2]) is set. if the amount of data available is greater than or equal to one word, a dma request is made to move all remaining whole words to the host by dma transfer. once the dma transfer is com- plete, a single remaining character causes an interrupt to the host to remove the character by reading pfhr2. this register is cleared by device or fifo reset. clearing it manually causes the stale bit to be true. 5.3.17 stale data timer period register this register provides a user-de?ed period value for use as the timeout value of the stale data timer (see sdtcr). with a 25-mhz clk input to the device, the resolution of this timer is 0.1 ms, its maximum value is 25.5 ms. the 25-mhz clock is divided by 250 to produce a 10- m s intermediate clock for this timer. a ?ed, divide-by-ten prescaler produces 0.1-ms ?icks to the stale data timer. the prescaler is reset each time the stale data timer is reloaded to ensure accuracy for small time-out values. (a user selection of a 0.1- ms timeout would result in a time delay of between 0.09 and 0.1 ms.) the sdtpr is cleared by device reset. register name: sdtcr register description: stale data timer count access: r/w 8-bit hex address: 3d default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit stale data timer count register name: sdtpr register description: stale data timer period access: r/w 8-bit hex address: 3c default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit stale data timeout value
data book v2.0 october 1996 62 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4 parallel port registers 5.4.1 epp address register this register is only used during epp mode. the cl-cd1283 deposits the value obtained during an epp address write command in this register. the cl-cd1283 provides this value in response to an epp address read command. 5.4.2 input value register this register always shows the current state of the external handshake pins. 5.4.3 manual data register this read/write register can read the state of the pd[7:0] signals in any mode. if the manmd bit (pcr[7])is set along with the mmdir and manoe bits (pcr[1:0]), then the value written into this register is driven onto the pd[7:0] signals. register name: ear register description: epp address access: r/w 8-bit hex address: 25 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit binary value register name: ivr register description: input value access: read only 8-bit hex address: 2e default value: xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 a1284 ninit hstbsy hstclk bit description 7:4 these read-only bits are always ?? 3 a1284 2 ninit: (active-low init input) 1 hstbsy: (host busy) 0 hstclk: (host clock) register name: mdr register description: manual data access: r/w 8-bit hex address: 21 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit binary data
october 1996 63 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.4 negotiation enable register each bit set along with e1284 (pcr[6]) allows the cl-cd1284 to engage in ieee std 1284 negotiations and move into the corresponding protocol. it is assumed that the peripheral host software responds to a request for slave id and is able to send an id string in any protocol that it supports. in response to an id request, the cl-cd1284 does not provide a method of storing and automatically sending an id string. note that the epp protocol does not have provision for slave id requests. register name: ner register description: negotiation enable access: r/w 8-bit hex address: 28 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 rid 0 epp rle ecp rvb rvn bit description 7 reserved: this read-only bit is always ?? 6 request slave id 5 reserved: this bit must always be ?? 4 epp mode enable 3 run length encoding in ecp mode enable 2 ecp mode enable 1 reverse byte mode enable 0 reverse nibble mode enable
data book v2.0 october 1996 64 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.5 negotiation status register the results of negotiation attempts are stored in this register. any change in the mode of the parallel port is reported to the peripheral host by interrupt if the negch bit is set in the pcier; host software then reads the nsr to determine the current status and condition. once the host has read the nsr status resulting from the current negotiation, it should clear the register in prep- aration for additional negotiation cycles. the nsr can be cleared by writing any value. register name: nsr register description: negotiation status access: r/w 8-bit hex address: 29 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 negok negfl hostto invalid 4-bit negotiation result code bit description 7 negok: the state of this bit indicates that the negotiation was successful. 6 negotiation failed: the state of this bit indicates that the negotiation failed. the result code indicates which mode attempted. 5 host timeout: this bit indicates that a host time-out occurred on the parallel channel. the accompanying 4-bit result code indicates that the link has returned to compatibility mode (x02). see description of htvr on page 53. 4 invalid: the state of this bit indicates that the state machine is in an invalid state due to the last negotiation sequence and has reentered compatibility mode 3:0 the lower 4 bits contain a result code, which shows the current mode. bits description 3210 0000 compatible mode ?no negotiation. 0001f ailed negotiation. 0010 compatible mode ?termination of a 1284 mode. 0011 reserved. 0100 0101 0110 epp mode. 0111 reserved. 1000rev erse nibble mode 1001rev erse nibble mode ?id request. 1010rev erse byte mode. 1011rev erse byte mode ?id request 1100 ecp mode without rle 1101 ecp mode without rle ?id request 1110 ecp mode with rle 1111 ecp mode with rle ?id request
october 1996 65 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.6 ones detect register setting the bits in this register enables the cl-cd1284 to generate an interrupt ?if sigch (pcier[4]) is set ?when the selected signal changes from low to high (rising edge). bits 7:4 are reserved and must be written as zeros; they return zero when read. the settings in this register have no effect (that is, sigch interrupt is not generated) unless the device is in manual mode. 5.4.7 output value register this register controls output signals. in manual mode, all signals are controlled by these register settings. in compatibility and epp modes, perbsy and perclk are controlled by the internal parallel port state machine while akdarq, xflag, and ndataav are controlled by this register. in ecp mode, the settings in this register have no effect. register name: odr register description: ones detect access: r/w 8-bit hex address: 2d default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 a1284 ninit hstbsy hstclk register name: ovr register description: output value access: write only 8-bit hex address: 2b default value: 48 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 perbsy perclk akdarq xflag ndatav 0 0 0 bit description 7 peripheral busy: user-controlled in manual mode only. 6 peripheral clock: user-controlled in manual mode only. 5 acknowledge data request: in compatible mode, this signal is the perror (peripheral error) signal. in epp mode, this signal is auxiliary and is a user-de?ed signal (user 1). 4 xflag: in compatible mode, this signal is the selct (select) signal. in epp mode, this signal is auxiliary and is a user-de?ed signal (user 2). 3 negative-true data available: in compatible mode, this signal is the nfault (negative-true fault) signal. in epp mode, this signal is auxiliary and is a user-de?ed signal (user 3). 2:0 reserved: these bits must be written as ??
data book v2.0 october 1996 66 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.8 parallel channel interrupt enable register 5.4.9 parallel channel interrupt status register the pcier and pcisr provide control and status of interrupts generated by the parallel channel control state machine. they have the same bit de?itions. each bit in the pcier enables the interrupt of the same type in the pcisr. a write of any value to the pcisr in response to an interrupt request, causes it to clear and the interrupt request to be removed. register name: pcier register description: parallel channel interrupt enable access: r/w 8-bit hex address: 22 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 timen negch sigch eppaw dirch idreq ninit register name: pcisr register description: parallel channel interrupt status access: r/w 8-bit hex address: 23 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 timovr negch sigch eppaw dirch idreq ninit bit description 7 reserved: this read-only bit is always ?? 6 timen/timovr: used for factory test purposes only. 5 negch: the state of this bit indicates that a change occurred in the negotiation status of the port. the nsr indicates the new status of the parallel port. 4 sigch: this bit instructs the parallel port to generate an interrupt when any of the signals speci?d by the zdr or odr change state as programmed. 3 eppaw: the state of this bit indicates that the remote master has written an epp address to the cl-cd1283. the new epp address value is placed in the ear. 2 dirch: this bit indicates that the host-side parallel port changed the direction of the interface. generally, this is in response to a request made by the cl-cd1283 through the revrq bit in the scr (bit 0). dirch indicates that the direction was reversed through the de?ed protocol and the cl-cd1283 can now send data to the master. this bit is only valid in ecp and epp (bidirectional) modes. 1 idreq: the state of this bit indicates that the host has requested that the cl-cd1283 send its id data string. the peripheral host should send the appropriate id string (this is application-dependent). 0 ninit: this interrupt is generated when an ninit pulse is received in compatibility mode. the interrupt occurs on the leading edge of the ninit pulse.
october 1996 67 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.10 parallel con?uration register this register controls the overall con?uration of the parallel port, each of which is described in ieee 1284 format below. register name: pcr register description: parallel configuration access: r/w 8-bit hex address: 20 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 manmd e1284 etxfr ig_sel htmrtst[1] htmrtst[0] mmdir manoe bit description 7:5 mode control: these three bits control the type of transfer desired and whether or not it is enabled to do so. the manmd bit selects manual mode, which allows the user direct control over all parallel data and parallel port control signals. mmdir controls the direction of the mdr (manual data register) and manoe is the out- put enable when mmdir = 1 (output mode). e1284 allows the parallel port to engage in ieee 1284 negotiations. etxfr enables data transfers. etxfr enable is only used for data transfers. epp address read and write functions do not require that the etxfr bit be set. 4 ig_sel: this bit prevents the cl-cd1284 from considering the state of the nslctin input when deciding whether or not to accept compatibility mode forward data transfers. when ig_sel is reset, nslctin must be active (low) to receive data on the parallel port in response to an nstrobe input. if ig_sel is set, nslctin is not considered and data is accepted regardless of its state. the ig_sel bit should be set/reset together with the e1284 bit. 3:2 host timer test control: these two bits control the clock rate of the host timeout timer and are intended primarily for manufacturing test purposes. as such, normal user-level programming should leave these bits cleared (??. when these bits are set to ?? the timer is completely disabled, this is useful for factory debug purposes. 1:0 manual mode control: these two bits provide direction and output enable manual control over the parallel port. manmd e1284 etxfr mode 0 0 0 compatibility mode; transfers disabled. 0 0 1 compatibility mode; transfers enabled. 0 1 0 ieee 1284 negotiation; transfers disabled. 0 1 1 ieee 1284 negotiation; transfers enabled. 1 x x manual mode. mmdir manoe mode 0 0 reverse direction. 0 1 reverse direction. 1 0 forward direction disabled. 1 1 forward direction enabled.
data book v2.0 october 1996 68 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.11 special command register this register allows the peripheral host processor to issue special commands to the channel control state- machine. in response, the state-machine will perform the indicated ieee std 1284-de?ed handshake on the parallel interface. register name: scr register description: special command access: r/w 8-bit hex address: 2a default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 testmux clrps setps epirq revrq bit description 7:5 these read-only bits are always ?? 4 testmux: when this bit is set, the state of the state machine is multiplexed onto the gpio pins for debug- ging purposes. gpio is not possible when this bit is set. 3:2 clear pause and set pause: the set and clear pause commands implement an error pause in compatibil- ity mode. usually, errors are presented to the host parallel port by the peripheral during the active busy period of a data transfer. setps remains set until clrps is set, at which time both will clear. in most cases, the slave host also sets revrq at the same time when setps is set to: 1) lockup compatibility mode with busy high, and 2) request a reverse transfer if the master requests that an additional status be sent in the reverse direction. 1 epp interrupt request: this command causes the state machine to generate the epp interrupt sequence. the epirq bit clears on the initiation of the intr (perclk) pulse on the parallel port interface. 0 reverse request: this command requests that the host parallel port initiate the de?ed interface reversal handshake as de?ed by the ieee std 1284 speci?ation. the command bit clears to indicate completion after the command has been executed on the interface. for reverse nibble and reverse byte modes, this occurs after negotiation is complete; in ecp mode, it occurs after the reverse request signal on the parallel port interface goes low. in ecp mode, nperiphrequest (nfault) is driven low to request that the host-side parallel port reverse the direction of the interface. when this bit is set upon termination to compatibility mode, the cl-cd1283 can indicate that reverse data is available (through the ndataav signal) immediately upon recognition of a reverse-nibble or reverse-byte negotiation. to obtain this behavior, this bit should be initialized to ?? and set to ? upon termination to com- patibility mode.
october 1996 69 data book v2.0 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.12 short pulse register this register performs two functions: 1) spr sets the duration of the short pulse used by the ieee 1284 protocols for all modes other than compat- ibility. 2) in compatibility mode, spr sets the duration of the ack* pulse. for non-compatibility modes, spr must be set to n - 2, where n is the number of clks in a 500-ns pulse. the peripheral host initializes spr with the appropriate value to generate a 500-ns pulse width based on the operating frequency of the device. in compatibility mode, spr should be set to the desired length of the ack* pulse. this is provided to enable the device to interface to slow masters that require an ack* pulse longer than the maximum spec- i?d in the ieee 1284 speci?ation. table 5-2 shows examples of the necessary binary value for various system clock frequencies to set the 500-ns pulse width. register name: spr register description: short pulse access: r/w 8-bit hex address: 26 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8-bit binary value table 5-2. spr binary values to set 500-ns pulse widths clock (mhz) spr value resultant pulse width (ns) 16 8 500 20 10 500 25 13 520
data book v2.0 october 1996 70 detailed register descriptions cl-cd1283 ieee 1284-compatible parallel interface controller 5.4.13 signal status register the bits in this register show the results of changes speci?d in the odr and zdr. normally, the host will read this register in response to a signal-change interrupt generated by the cl-cd1283. ssr is active and valid only in manual mode. bits 7:4 return zeros when read. a write of any value to ssr clears it. 5.4.14 zeros detect register when the bits 3:0 in zdr are set, it enables the cl-cd1283 to generate an interrupt (if the sigch bit in pcier is set) when the selected signal changes from high-to-low (falling edge). bits 7:4 are reserved and must be written as ?? these bits return ? when read. this register is enabled only during manual mode. 5.5 special register 5.5.1 reset command register this special-purpose register allows the local cpu to issue a hard reset of the device through software. the rcr performs the same function as the ccr in the cl-cd1283, except that the only command avail- able is the reset command. to maintain binary compatibility with the cl-cd1284, the cl-cd1283 places the rcr in the address space of either of the two serial channels in the cl-cd1284. thus, before issuing the reset command, the local cpu must select either channel 2 or 3 through the aer. once that is accomplished, a write of hex 81 to the rcr initiates the internal reset. the local cpu must wait for the gfrcr to become valid before beginning operation with the device. register name: ssr register description: signal status access: r/w 8-bit hex address: 2f default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 a1284 ninit hstbsy hstclk register name: zdr register description: zero detect access: r/w 8-bit hex address: 2c default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 a1284 ninit hstbsy hstclk register name: rcr register description: reset command access: r/w 8-bit hex address: 05 default value: 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10000001
october 1996 71 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller 6. electrical specifications 6.1 absolute maximum ratings supply voltage (v cc ) ............................................................................................................................... ............ + 7.0 v (volts) input voltages, with respect to ground ................................................................................................ - 0.5 v to v cc + 0.5 v operating temperature (t a )......................................................................................................................0 c to 70 c storage temperature ............................................................................................................................... ......... - 65 c to 150 c power dissipation .............................................................................................................. .................... 0.25 w (watt) note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any conditions above those indicated in the recommended operating conditions is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.2 recommended operating conditions supply voltage (v cc ).............................................................................................................................. ...... 5 v 5% operating free air ambient temperature ......................................................................................... .. 0 c < t a < 70 c system clock ................................................................................................................... ............................... 25 mhz 6.3 dc characteristics esd (human body model) 100 pf, 1.5 k w , 2 kv mil-std-883d method 3015.7 esd (machine model) 200 pf, 0 w , 200 v eiaj ic-121 latch-up i/o 100 ma, v cc = 5 v temperature = 25 c and 70 c jedec number 17 v cc ramp 5 v to 9 v temperature = 25 c and 70 c jedec number 17 hysteresis 200 mv before beginning any new design with this device, please contact cirrus logic for the latest errata information. this data book is in reference to revision e or newer devices. see the back cover of this document for sales of?e locations and phone numbers.
data book v2.0 october 1996 72 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller the signals speci? to the parallel port meet all requirements of the ieee std 1284 speci?ation, except for input signal protection ( - 2.0 to + 7.0 v); external circuitry is required to meet this speci?ation. note: while the cl-cd1283 is a highly dependable device, there are a few guidelines to ensure that the maximum possible level of overall system reliability is achieved. first, design the pc board to provide maximum iso- lation of noise. a four-layer board is preferable, but a two-layer board will work if proper power and ground distribution is implemented. in either case, decoupling capacitors mounted close to the cl-cd1283 are strongly recommended. noise typically occurs when either the cl-cd1283 data bus drivers come out of tristate to drive the bus during a read, or when an external bus buffer turns on during a write cycle. this noise, a rapid rate-of-change of supply current, causes ?round bounce in the power-distribution traces. this ground bounce, a rise in the voltage of the ground pins, effectively raises the input logic thresholds of all devices in the vicinity, resulting in the possibility of a ? being interpreted as a ?? to reduce the possibility of ground-bounce affecting the operation of the cl-cd1283, cirrus logic has spec- i?d the input-high voltage (v ih ) of the clk and reset* pins at 2.7 v, instead of the ttl-standard 2.0 v. this eliminates any sensitivity to ground bounce, even in extremely noisy systems. although 2.7 v is higher than the industry-standard 2.4-v output (v oh ) speci?d for ttl, there are several simple ways to meet this speci?ation: 1) use any of the available advanced-cmos logic families (fact, acl, and so on). these cmos output buffers will pull-up close to v cc when not heavily loaded. in addition, as and als ttl can be used if the output of the ttl device is only driving one or two cmos loads. 2) as noted in the texas instruments als/as logic data book (1986 ?pages 4-18 and 4-19), the v oh output of these families exceeds 3.0 v at low-current loading. other manufacturers publish similar data. cirrus logic recommends the use of one of these two options for the clk input to ensure fast, clean edges. note that reset* can, if desired, be pulled up passively with 1-k w resistor. a v ih is 2.7 v minimum on reset* and clk. b v ol for open-drain signals is 0.5 v @ 8 ma sinking because these signals can be wire-or?d in some systems and can have multiple pull-up resistors that increase the load on the output. (@ v cc = 5 v 5%, t a = 0 c to 70 c) symbol parameter min max units test conditions v il input low voltage - 0.5 0.8 v v ih input high voltage 2.0 v cc v a v ol output low voltage 0.4 v i ol = 2.4 ma b v oh output high voltage 2.4 v i oh = - 400 m a i il input leakage current - 10 10 m a0 < v in < v cc i ll data bus tristate leakage current - 10 10 m a0 < v out < v cc i oc open-drain output leakage current - 10 10 m a0 < v out < v cc i cc power supply current 50 ma clk = 25 mhz c in input capacitance 10 pf c out output capacitance 10 pf symmetrical input/output drive: 14 ma controlled voltage slew rate: 0.4 v/ m s input hysteresis: 0.8 v
october 1996 73 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller 6.4 ac characteristics 6.4.1 asynchronous timing refer to figures 6-1 through 6-7b for the reference numbers in table 6-1. (@ v cc = 5 v 5%, t a = 0 c to 70 c) table 6-1. asynchronous timing reference parameters timing no. figure parameter min max unit t 1 6-1 reset* a low pulse width 10 t clk t 2 6-3 address setup time to cs* or ds* 10 ns t 3 6-3 r/w* setup time to cs* or ds* 10 ns t 4 6-3 address hold time after cs* 0 ns t 5 6-3 r/w* hold time after cs* 0 ns t 6 6-3 dtack* low to read data valid 10 ns t 7 6-3 dtack* low from cs* or ds b 2 t clk 4 t clk + 30 ns t 8 6-3 data bus tristate after cs* or ds* high 0 30 ns t 9 6-3 cs* or dgrant* high from dtack* low 0 ns t 10 6-3 dtack* inactive from cs* or dgrant* and ds* high 40 ns t 11 6-3 ds* high pulse width 10 ns t 12 6-4 write data valid from cs* and ds* low 1t clk ns t 13 6-4 write data hold time after ds* high 0 ns t 14 6-2 clock period (t clk ) a, c 40.0 1000 ns t 15 6-2 clock low time a 0.3 t clk 0.7 t clk ns t 16 6-2 clock high time a 0.3 t clk 0.7 t clk ns t 17 6-5 propagation delay, dgrant* and ds* to dpass* 35 ns t 18 6-5 setup time, svcack* to ds* and dgrant* 10 ns t 19 6-6a setup time, dmaack* to rising edge of clk 10 ns t 20 6-6a hold time, read data after rising edge of clk 10 30 ns t 21 6-7a setup time, write data to rising edge of clk 0 ns t 22 6-3 dtack* active pull-up time d ns t 23 6-6a data valid after falling edge of clk (dma read) 25 ns t 24 6-6a 6-7a hold time, dmareq* after dmaack* falling edge, last dma cycle 10 1 clk + 15 ns
data book v2.0 october 1996 74 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller a timing numbers for reset* and clk are valid for both asynchronous and synchronous speci?ations. the device will operate on any clock with a 40?0 or better duty cycle. b on host-i/o cycles, immediately following svcack* cycles and writes to eosrr, dtack* will be delayed by 20 clks (1 ms @ 20 mhz; 800 ns @ 25 mhz). on systems that do not use dtack* to signal the end of the i/o cycle, wait states or some other form of delay generation must be used to assure that the cl-cd1283 is not accessed until after this time period. c as tclk increases, device performance decreases. a minimum clock frequency of 25 mhz is required to guarantee speci?d performance. the recommended maximum tclk is 1000 ns. d dtack* sources current (drives ?igh? until the voltage on the dtack* line is approximately 1.5 v; then dtack* goes to the ?pen-drain (high-impedance) state. the following timing numbers are for the back-to-back asynchronous dma timing diagrams. t 25 6-6b hold time, dmaack* active (dma read/write) 3 clk t 26 6-6b delay, data valid after falling edge dmaack* (dma read) 0.5 clk + 20 1.5 clk + 25 ns t 27 6-6b hold time, data valid after rising edge dmaack* (dma read) 10 30 ns t 28 6-6b 6-7b inactive time, dmaack* (dma read/write) 10 ns t 29 6-6b 6-7b hold time, dmareq* rising edge after dmaack* falling edge (dma read/write) 10 1 clk + 15 ns t 30 6-7b hold time, dmaack* active (dma write) 2.5 clk t 31 6-7b delay, data valid after falling edge dmaack* (dma write) 1.5 clk table 6-1. asynchronous timing reference parameters (cont.) timing no. figure parameter min max unit
october 1996 75 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-1. reset timing note: for synchronous systems, it is necessary to determine the clock cycle number so that interface circuitry can stay in lock-step with the device. clk numbers can be determined if reset* is released within the range t a ? b ; t a is de?ed as 10 ns minimum, after the rising edge of the clock; t b is de?ed as 5 ns minimum, before the next rising edge of the clock. if these conditions are met, the cycle starting after the second rising edge will be c1. see the synchronous timing diagrams for additional information. clock numbers are not impor- tant in asynchronous systems. . figure 6-2. clock timing t 1 v cc clk reset* t a t b c2 c1 c2 c1 c2 clk/2 t 14 t 16 t 15 clk
data book v2.0 october 1996 76 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-3. asynchronous read cycle timing a[6:0] r/w* cs* dtack* db[15:0] t 11 t 2 t 4 t 3 t 6 t 7 t 10 t 9 t 8 t 5 ds* t 22
october 1996 77 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-4. asynchronous write cycle timing a[6:0] r/w* dtack* db[15:0] t 2 t 4 t 3 t 12 t 7 t 10 t 9 t 13 t 5 cs* ds* t 22
data book v2.0 october 1996 78 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-5. asynchronous service acknowledge cycle timing t 2 t 4 t 3 t 5 t 11 t 18 t 6 t 8 t 9 t 10 t 17 t 7 t 22 a[6:0] r/w* svcack* dgrant* dtack* db[15:0] dpass* ds* svcreq*
october 1996 79 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-6a. asynchronous dma read cycle timing figure 6-6b. asynchronous dma read cycle timing (two back-to-back dma reads) t 20 t 23 t 24 t 19 db[15:0] dmaack* clk ? ? notes: 1) the dma handshake operates in asynchronous mode only if the asyncdma bit is set in pacr. 2) if dmaack* is released after point ?, but before point ? (two rising clk edges after the falling edge of dmaack*), db[15:0] is released at t 20 following the rising edge of clk. if dmaack* is held past this edge, it controls the release of db[15:0]; the data bus remains active until dmaack* becomes inactive (point ??. 3) this figure 6-6a is still valid, however, figure 6-6b illustrates a more robust timing. ? may change valid dmareq* db[15:0] dmaack* clk note: the falling edge of dmaack* is synchronized internally with the rising edge of the clock when asynchronous timing is selected by pacr[1]. the data valid time can vary by as much as one full clk cycle depending on when dmaack* falling edge occurs in relation to the clk rising edge. the minimum dmaack* active time must be met to ensure that the data has become valid before the rising edge of dmaack*. the dmaack* can be extended to any length, which extends the data valid hold time accordingly. if t 25 is not met and dmaack* is deasserted in less than t 25 (min), then the data bus tristates t 27 after the third rising clock edge following the assertion of dmaack*. t 27 t 29 valid dmareq* see note see note t 28 t 25 valid t 26 dmaack* synchronized here
data book v2.0 october 1996 80 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-7a. asynchronous dma write cycle timing figure 6-7b. asynchronous dma write cycle timing t 24 t 24 t 19 clk dmaack* db[15:0] may change valid dmareq* note: this figure 6-7a is still valid, however, figure 6-7b illustrates a more robust timing. db[15:0] dmaack* clk note: the data is sampled on the third rising edge of clk following the assertion of dmaack*. if dmaack* is held active for more than three clk cycles then the next dma write cycle will simply be delayed, but the data will still be sampled on the third rising clk edge following the assertion of dmaack*. if dmaack* is active for < 3 clks, the n the data is still sampled on the third rising clk edge following the assertion of dmaack* (provided that dmaack* is active long enough for the device to lastch it. due to this somewhat synchronous behavior, care must be taken to guarantee that the data is valid at this clk edge. do not assume that the data will be sampled on the deassertion of dmaack*. t 32 t 29 valid dmareq* t 28 valid t 31 t 30 t 30 t 32 t 31 dmaack* synchronized here dmaack* synchronized here data sampled here data sampled here dmaack* latched here see note
october 1996 81 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller 6.4.2 synchronous timing use the following table as a reference to timing parameters of figures in this section. a on host i/o cycles immediately following svcack* cycles and writes to the eosrr, dtack* will be delayed by 20 clks (1 ms @ 20 mhz, 800 ns @ 25 mhz). on systems that do not use dtack* to signal the end of the i/o cycle, use wait states or some other form of delay generation to assure that the cl-cd1283 is not accessed until after this time period. b dtack* sources current (drives ?igh? until the voltage on the dtack* line is approximately 1.5 v; then dtack* enters the ?pen-drain (high-impedance) state. table 6-2. synchronous timing reference parameters timing number figure parameter min max unit t 1 6-8 setup time, cs* and ds* to c1 rising edge 15 ns t 2 6-8 setup time, r/w* to c1 rising edge 15 ns t 3 6-8 setup time, address valid to c1 rising edge 20 ns t 4 6-8 c2 rising edge to data valid 60 ns t 5 6-8 dtack* low from c3 rising edge a 30 ns t 6 6-8 cs* and ds* trailing edge to data bus high-impedance 30 ns t 7 6-8 cs* and ds* inactive between host accesses 10 ns t 8 6-8 hold time, r/w* after c3 rising edge 20 ns t 9 6-8 hold time, address valid after c3 rising edge 0 ns t 10 6-9 setup time, write data valid to c2 rising edge 0 ns t 11 6-10 setup time, ds* and dgrant* to c1 rising edge 30 ns t 12 6-10 setup time, svcack* to ds* and dgrant* 10 ns t 13 6-9 hold time, write data valid after c3 rising edge 0 ns t 14 6-11 propagation delay, ds* and dgrant* to dpass* 35 ns t 15 6-11 6-12 falling edge dmareq* after rising edge clk (dma write/read) 25 ns t 16 6-11 6-12 hold time, rising edge dmareq* after falling edge dmaack* (dma write/read) 20 ns t 17 6-11 setup time, data valid before rising edge c3 (dma write) 5 ns t 18 6-11 6-12 setup time, falling edge dmaack* to falling edge c1 (dma write/read) 10 ns t 21 6-8 dtack* active pull-up time b t 22 6-12 hold time, data valid after rising edge c3 (dma write) 5 t 23 6-12 hold time, data valid after rising edge c1 (dma read) 10 30 t 24 6-12 data valid after falling edge c1 (dma read) 25 t 25 6-12 inactive time, dmaack* (dma read) 10
data book v2.0 october 1996 82 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-8. synchronous read cycle timing t 1 t 2 t 3 t 4 t 8 t 9 t 6 c1 c2 c3 clk ds*, cs* r/w* a[6:0] db[15:0] dtack* t 5 t 7 t 21
october 1996 83 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-9. synchronous write cycle timing t 1 t 2 t 3 t 8 t 9 t 13 c1 c2 c3 clk ds*, cs* r/w* a[6:0] db[15:0] dtack* t 5 t 10 t 7 t 21
data book v2.0 october 1996 84 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-10. synchronous service acknowledge cycle timing t 12 t 2 t 4 t 8 t 6 c1 c2 c3 clk ds*, dgrant* r/w* db[15:0] dtack* t 5 t 7 svcackp* t 11 t 21 svcreq* dpass* t 14
october 1996 85 data book v2.0 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-11. synchronous dma write cycle timing (two back-to-back 3-cycle dma writes) db[15:0] dmaack* clk note: the data is sampled on the second rising edge of clk following the assertion of dmaack*, as long as setup time (t 18 ) is met. if dmaack* is held active for more than 2.5 clk cycles then the next dma cycle is simply delayed, but the data is still sampled on the second rising clk edge following the assertion of dmaack*. t 16 valid dmareq* t 18 valid c c1c2c3 c1c2c3c data sampled here t 15 t 25 t 17 t 22 t 22 t 17 data sampled here see note see note
data book v2.0 october 1996 86 electrical specifications cl-cd1283 ieee 1284-compatible parallel interface controller figure 6-12. synchronous dma read cycle timing (two back-to-back 3-cycle dma reads) db[15:0] dmaack* clk note: the data is sampled on the second rising edge of clk following the assertion of dmaack*, as long as setup time (t 18 ) is met. if dmaack* is held active for more than 2.5 clk cycles then the next dma cycle is simply delayed, but the data is still sampled on the second rising clk edge following the assertion of dmaack*. valid dmareq* t 18 valid c c1c2c3 c1c2c3c t 15 see note see note t 25 t 18 t 24 t 16 t 23
october 1996 87 data book v2.0 package dimensions cl-cd1283 ieee 1284-compatible parallel interface controller 7. package dimensions notes: 1) dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) before beginning any new design with this device, please contact cirrus logic for the latest package information. pin 1 indicator pin 1 19.90 (0.783) 22.95 (0.904) 23.45 (0.923) 20.10 (0.791) 16.95 (0.667) 17.45 (0.687) 13.90 (0.547) 14.10 (0.555) 0.13 (0.005) 0.23 (0.009) 1.60 (0.063) ref 2.57 (0.101) 2.87 (0.113) 0.65 (0.026) 0.95 (0.037) 0 min 7 max 0.22 (0.009) 0.38 (0.015) 0.65 (0.0256) bsc pin 100 3.40 0.25 (0.134) max (0.010) min cl-cd1283 100-pin pqfp (jedec)
data book v2.0 october 1996 88 ordering information cl-cd1283 ieee 1284-compatible parallel interface controller 8. ordering information the order number for the cl-cd1283 is: cl ?cd1283 ?10qc ?e cirrus logic inc. product line: part number internal reference number package type: temperature range: revision ? c = commercial q = quad ?t pack (in plastic package) ? contact cirrus logic for up-to-date information on revisions. communications, data
october 1996 89 data book v2.0 bit index cl-cd1283 ieee 1284-compatible parallel interface controller numerics 4-bit negotiation result code 64 6-bit binary fifo pointer value 57 7-bit unsigned binary count 60 8-bit binary data 62 8-bit binary value 62, 69 8-bit character data 58 8-bit stale data timeout value 61 8-bit stale data timer count 61 a a1283 62 a1284 65, 70 asyncdma 55 b bufrderr 50 bufwrerr 50 c clearto 55 clrps 31, 68 ctnot0 52 d data or space available in fifo 58 data[7:0] 45 dataerr 59 dir[7:0] 45 dirch 66 dma buffer data 51 dma transfer threshold 60 dmaact 52 dmabufwe 57 dmadir 56 dmaen 56 dmafull 52 dmampty 52 dmarderr 50 dmareq 47 dmawrerr 50 e e1284 31, 67 epirq 31, 68 eppaw 66 erren 57 etxfr 31, 67 f ffempty 27, 59 fffull 59 fifolock 31, 55 fifores 56 firmware revision code 44 h hostto 64 hr1full 52 hr1rderr 50 hr1tag 52 hr1wrerr 50 hr2full 52 hr2rderr 50 hr2tag 52 hr2wrerr 50 hrdata 59 hrtag 59 hstbsy 62, 65, 70 hstclk 62, 65, 70 htmrtst[1:0] 67 i idreq 32, 66 ig_sel 67 inten 57 invalid 64 m manmd 30, 67 manoe 67 mmdir 30, 67 n negch 66 negfl 31 negfl 64 negok 31, 64 ninit 66 ninit 62, 65, 70 o onechar 28, 59 bit index
data book v2.0 october 1996 90 bit index cl-cd1283 ieee 1284-compatible parallel interface controller p pchreset 56 pipeline 46 ppireq 46 pport 46 r revrq 31, 68 rleen 26, 57 s setps 31, 68 settag 57 shrtstal 55 shrtten 55 sigch 66 srp 47 stale 27, 59 staleoff 27, 55 t timeout 27, 59
october 1996 91 data book v2.0 index cl-cd1283 ieee 1284-compatible parallel interface controller a abbreviations 7 absolute maximum ratings 71 ac characteristics 73 acronyms 7 ascii code tables decimal 43 hexadecimal 43 b bus interface 26 byteswap 26 c cable connection 34 compatibility mode status 31 compatibility mode. see modes context 25 context switch hardware-activated 25 software-activated 25 control signal generation 24 control signals 30 conventions 7 cpu interface 16, 35 cycles dma cycles 18 service-acknowledge cycles 17 d daisy-chaining 20 data pipeline 25 data transfers 31 dc characteristics 71 decimal code tables 43 de?itions host 29 master 29 peripheral 29 slave 29 device architecture 16 device reset 38 dma cycles. see cycles e ecp mode 26 ecp modes. see modes electrical speci?ations 71 endian format 18 epp mode 30 epp mode. see modes external buffer control 35 f failed negotiation 31 fifo data path receive 29 transmit 30 functional block diagram 16 functional description 16 g general-purpose i/o port 33 h hardware con?urations interfacing to a motorola microprocessor-based system 37 interfacing to an intel microprocessor-based system 36 hardware-activated context switch. see context switch 25 hexadecimal code tables 43 i id request 32 ieee standards department 26 ieee std 1284 26, 29 ieee std 1284 protocol negotiations 31 initialization, cl-cd1283 38 intel 80x86 family interface. see interface interface 26 intel 80x86 family 36 motorola 68020 37 parallel port 31, 33 internal address generation 17 interrupts 19, 30 dirch 24 eppaw 21 idreq 24 negch 21 invalid termination 31 ivr 30 index
data book v2.0 october 1996 92 index cl-cd1283 ieee 1284-compatible parallel interface controller m modes compatibility 31 ecp 26, 32 epp 30, 33 manual 30 reverse byte 32 reverse nibble 32 motorola 68020 interface. see interface o odd-byte transfers 18 odr 30 operating conditions 71 ordering information 88 p package dimensions 87 parallel pipeline registers. see registers parallel port 26, 29 con?uration 29 fifo 25?6 interface. see interface overview 29 service requests 21 signal names 29 state machine 29 terminology 29 parallel port registers. see registers parallel protocol support 32 pin information 8 pin descriptions 10 pin diagram 8 pin list 9 protocol negotiations 31 protocol timing 33 r read cycles 17 receive direction 27 receiving compressed data 27 register descriptions 44?0 register map 13 register summary 13 registers channel ?parallel htvr 14 global aer 44 car 13 gfrcr 13, 44 gpdir 13, 45 gpio 13, 45 pir 13, 46 ppr 13, 46 svrr 13, 47 parallel pipeline der 14, 50 dmabuf 14, 51 hrsr 14, 52 livr 14, 54 pac r 14, 55 pcrr 14, 56 pfcr 14, 56 pfep 14, 57 pffp 14, 57 pfhr1 14, 58 pfhr2 14, 58 pfqr 14, 58 pfsr 14, 59 pftr 14, 60 rlcr 14, 60 sdtcr 14, 61 sdtpr 14, 61 parallel port ear 15, 62 ivr 15, 62 mdr 15, 62 ner 15, 63 nsr 15, 31, 64 odr 15, 65 ovr 15, 65 pcier 15, 66 pcisr 15, 66 pcr 15, 67 scr 15, 31, 68 spr 15, 69 ssr 15, 70 zdr 15, 70 special rcr 70 virtual eosrr 14, 48 pivr 14, 49 reset, device 38 rle (run-length-encoding) 27 s sample system block diagram 35 service-acknowledge cycles. see cycles signal names 29 software-activated context switch. see context switch special register. see registers
october 1996 93 data book v2.0 index cl-cd1283 ieee 1284-compatible parallel interface controller ssr 30 stale data timer 27 state machine 29 svcreqp* 49 synchronous timing reference parameters 81 t timing asynchronous 73 clock 75 dma read cycle 79 read cycle 76 reset 75 service acknowledge cycle 78 write cycle 77 synchronous 81 read cycle 82 service acknowledge cycle 84 write cycle 83 transmit direction 28 u units of measure used 7 v virtual registers. see registers w write cycles 17 z zdr 30
data book v2.0 october 1996 94 cl-cd1283 ieee 1284-compatible parallel interface controller notes
october 1996 95 data book v2.0 cl-cd1283 ieee 1284-compatible parallel interface controller notes
cirrus logic inc. publications ordering: 800/359-6414 (usa) or 510/249-4200 3100 west warren ave., fremont, ca 94538 world wide web: http://www.cirrus.com tel: 510/623-8300 fax: 510/252-6020 541283-002 cl-cd1283 data book v2.0 direct sales of?es the company headquartered in fremont, california, cirrus logic is a leading manufacturer of advanced integrated circuits for desktop and portable computing, telecommunications, and consumer electronics. the company applies its system- level expertise in analog and digital design to innovate highly integrated, software-rich solutions. cirrus logic has developed a broad portfolio of products and technologies for applications spanning multimedia, graphics, communications, system logic, mass storage, and data acquisition. the cirrus logic formula combines innovative architectures in silicon with system design expertise. we deliver complete solutions ?chips, software, evaluation boards, and manufacturing kits ?on-time, to help you win in the marketplace. cirrus logic? manufacturing strategy ensures maximum product quality, availability, and value for our customers. talk to our systems and applications specialists; see how you can bene? from a new kind of semiconductor company. copyright ? 1996 cirrus logic inc. all rights reserved. cirrus logic inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. how ever, the information is subject to change without notice. no responsibility is assumed by cirrus logic inc. for the use of this information, nor for in fringements of patents or other rights of third parties. this document is the property of cirrus logic inc. and implies no license under patents, copyrights, o r trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, m echanical, photographic, or otherwise, or used as the basis for manufacture or sale of any items without the prior written consent of cirrus logic inc. ci rrus logic, accupak, compactcard, compactstor, diva, fastpath, featurechips, good data, laguna, mediadac, motionvideo, simulscan, s/la, softarget, t exturejet, tvtap, uxart, visualmedia, v-port, and waveport are trademarks of cirrus logic inc., which may be registered in some jurisdicti ons. other trademarks in this document belong to their respective companies. crus and cirrus logic international, ltd. are trade names of cirrus logi c inc. domestic n. california fremont tel: 510/623-8300 fax: 510/252-6020 s. california irvine tel: 714/453-5961 fax: 714/453-5962 westlake village tel: 805/371-5860 fax: 805/371-5861 south central area austin, tx tel: 512/255-0080 fax: 512/255-0733 dallas, tx tel: 214/252-6698 fax: 214/252-5681 houston, tx tel: 713/257-2525 fax: 713/257-2555 northeastern area andover, ma tel: 508/474-9300 fax: 508/474-9149 southeastern area duluth, ga tel: 770/935-6110 fax: 770/935-6112 raleigh, nc tel: 919/859-5210 fax: 919/859-5334 boca raton, fl tel: 407/241-2364 fax: 407/241-7990 international f rance paris tel: 33/1-48-12-2812 fax: 33/1-48-12-2810 germany munich tel: 49/81-52-40084 fax: 49/81-52-40077 hong kong tsimshatsui tel: 852/2376-0801 fax: 852/2375-1202 italy milan tel: 39/2-3360-5458 fax: 39/2-3360-5426 japan tokyo tel: 81/3-3340-9111 fax: 81/3-3340-9120 korea seoul tel: 82/2-565-8561 fax: 82/2-565-8565 singapore tel: 65/743-4111 fax: 65/742-4111 taiwan taipei tel: 886/2-718-4533 fax: 886/2-718-4526 united kingdom london, england tel: 44/1727-872424 fax: 44/1727-875919

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